Texas Instruments OMAP5912 Reference Manual page 1638

Figure 8. Example of Clock Signal Control of Bit Transfer Timing
Internal
CLK(R/X)
Internal
FS(R/X)
A1
D(R/X)
2.3.2 Serial Words
2.3.3 Frames and Frame Synchronization
SPRU762B
In the example in Figure 8, the clock signal controls the timing of each bit
transfer on the pin.
A0
Á Á
Note:
The McBSP cannot operate at a frequency faster than 1/2 the CPU clock fre-
quency. When driving CLKX or CLKR at the pin, choose an appropriate input
clock frequency. When using the internal sample rate generator for CLKX
and/or CLKR, choose an appropriate input clock frequency and divide down
value (CLKDV).
Bits traveling between a shift register (RSR or XSR) and a data pin (DR or DX)
are transferred in a group called a serial word. You can define how many bits
are in a word.
Bits coming in on the DR pin are held in RSR until RSR holds a full serial word.
Only then is the word passed to RBR (and ultimately to the DRR).
During transmission, XSR does not accept new data from DXR until a full serial
word has been passed from XSR to the DX pin.
In the example in Figure 8, an 8-bit word size was defined (see bits 7 through
0 of word B being transferred).
One or more words are transferred in a group called a frame. You can define
how many words are in a frame.
All of the words in a frame are sent in a continuous stream. However, there can
be pauses between frame transfers. The McBSP uses frame-synchronization
signals to determine when each frame is received/transmitted. When a pulse
occurs on a frame-synchronization signal, the McBSP begins receiving/trans-
mitting a frame of data. When the next pulse occurs, the McBSP
receives/transmits the next frame, and so on.
B7 B6 B5 B4 B3
Multichannel Buffered Serial Ports (McBSPs)
McBSP Operation
B2 B1 B0
Á
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