Texas Instruments OMAP5912 Reference Manual page 1633

McBSP Operation
Introduction to McBSPs / McBSP Operation
Table 1. McBSP Interface Pins (Continued)
Pin McBSP1
DX MCBSP1.DX
FSR
FSX MCBSP1.FSX
1.4 McBSP Register Addresses
2 McBSP Operation
2.1 Data Transfer Process of McBSPs
22 Multichannel Buffered Serial Ports (McBSPs)
McBSP2 McBSP3
MCBSP2.DX MCBSP3.DX
MCBSP2.FSR
MCBSP.FSX MCBSP3.FSX
See section 13, McBSP Registers, for McBSP register memory maps and
detailed register descriptions.
This section addresses the following topics:
Data transfer process
-
Clocking and framing data
-
Frame phases
-
McBSP reception
-
McBSP transmission
-
Interrupts and DMA events generated by McBSPs
-
Figure 3 shows a diagram of the McBSP data transfer paths. The McBSP
receive operation is triple-buffered, and transmit operation is double-buffered.
The use of registers varies, depending on whether the defined length of each
serial word is 16 bits.
Direction Possible Uses
O Transmitting
general-purpose output
I/O Supplying or reflecting the
receive frame-sync
controlling sample rate gener-
ator synchronization, when
GSYNC = 1
3.3); general-purpose I/O
I/O Supplying or reflecting the
transmit frame-sync signal;
general-purpose I/O
serial data;
signal;
(see section
SPRU762B