Texas Instruments OMAP5912 Reference Manual page 1651

McBSP Sample Rate Generator
3.1.4 Keeping CLKG Synchronized to an External Input Clock
3.2 Frame Synchronization Generation in the Sample Rate Generator
40 Multichannel Buffered Serial Ports (McBSPs)
The first divider stage of the sample rate generator creates the output clock
from the input clock. This divider stage uses a counter that is preloaded with
the divide down value in the CLKGDV bits of SRGR1. The output of this stage
is the data clock (CLKG). CLKG has the frequency represented by the
following equation.
Input clock frequency
CLKG frequency +
Thus, the input clock frequency is divided by a value between 1 and 256. When
CLKGDV is odd or equal to 0, the CLKG duty cycle is 50%. When CLKGDV
is an even value, 2p, representing an odd divide down, the high-state duration
is p+1 cycles and the low-state duration is p cycles.
Note:
The McBSP cannot operate at a frequency faster than 1/2 the CPU clock fre-
quency. Choose an input clock frequency and a CLKDV value such that
CLKG is less than or equal to 1/2 the CPU clock frequency.
When an external signal is selected to drive the sample rate generator (see
section 3.1.1), the GSYNC bit in SRGR2 and the FSR pin can be used to
configure the timing of the output clock (CLKG) relative to the input clock.
GSYNC = 1 ensures that the McBSP and an external device are dividing down
the input clock with the same phase relationship. If GSYNC = 1, an
inactive-to-active transition on the FSR pin triggers a resynchronization of
CLKG and generation of FSG.
For more details about synchronization, see section 3.3.
The sample rate generator can produce a frame-synchronization signal (FSG)
for use by the receiver, the transmitter, or both.
If you want the receiver to use FSG for frame synchronization, make sure
FSRM = 1. (When FSRM = 0, receive frame synchronization is supplied via
the FSR pin.)
( CLKGDV ) 1 )
SPRU762B