Texas Instruments OMAP5912 Reference Manual page 1641

McBSP Operation
2.4 Frame Phases
2.4.1 Number of Phases, Words, and Bits Per Frame
Table 2. McBSP Register Bits
Operation Number of Phases
Reception 1 (RPHASE = 0)
Reception 2 (RPHASE = 1)
Transmission 1 (XPHASE = 0)
Transmission 2 (XPHASE = 1)
30 Multichannel Buffered Serial Ports (McBSPs)
The McBSP supports operation of the serial port in this fashion by ignoring the
successive frame-synchronization pulses. Data is clocked into the receiver or
clocked out of the transmitter during every clock cycle.
Note:
For XDATDLY = 0 (0-bit data delay), the first bit of data is transmitted asyn-
chronously to the internal transmit clock signal (CLKX). For more details, see
section 8.12, Set the Transmit Data Delay.
The McBSP allows you to configure each frame to contain one or two phases.
The number of words per frame and the number of bits per word can be
specified differently for each of the two phases of a frame, allowing greater
flexibility in structuring data transfers. For example, a user might define a
frame as consisting of one phase containing two words of 16 bits each,
followed by a second phase consisting of 10 words of 8 bits each. This
configuration permits the user to compose frames for custom applications or,
in general, to maximize the efficiency of data transfers.
Table 2 shows which bit-fields in the receive control registers (RCR1 and
RCR2) and in the transmit control registers (XCR1 and XCR2) determine the
number of phases per frame, the number of words per frame, and number of
bits per word for each phase, for the receiver and transmitter. The maximum
number of words per frame is 128 for a single-phase frame and 256 for a
dual-phase frame. The number of bits per word can be 8, 12, 16, 20, 24, or 32
bits.
Words per Frame
Set With
RFRLEN1
RFRLEN1 and RFRLEN2
XFRLEN1
XFRLEN1 and XFRLEN2
Bits per Word
Set With
RWDLEN1
RWDLEN1 for phase 1
RWDLEN2 for phase 2
XWDLEN1
XWDLEN1 for phase 1
XWDLEN2 for phase 2
SPRU762B