Texas Instruments OMAP5912 Reference Manual page 1683

SPI Operation Using the Clock Stop Mode
6.2 Clock Stop Mode
6.3 Bits Used to Enable and Configure the Clock Stop Mode
72 Multichannel Buffered Serial Ports (McBSPs)
The master device controls the flow of communication by providing shift-clock
and slave-enable signals. The slave-enable signal is an optional active-low
signal that enables the serial data input and output of the slave device, or the
device not sending out the clock.
In the absence of a dedicated slave-enable signal, communication between
the master and slave is determined by the presence or absence of an active
shift-clock. When the McBSP is operating in SPI master mode and the SS*
signal is not used by the slave SPI port, the slave device must remain enabled
at all times, and multiple slaves cannot be used.
The clock stop mode of the McBSP provides compatibility with the SPI
protocol. When the McBSP is configured in clock stop mode, the transmitter
and receiver are internally synchronized so that the McBSP functions as an
SPI master or slave device. The transmit clock signal (CLKX) corresponds to
the serial clock signal (SCK) of the SPI protocol, while the transmit
frame-synchronization signal (FSX) is used as the slave-enable signal (SS_).
The receive clock signal (CLKR) and receive frame-synchronization signal
(FSR) are not used in the clock stop mode because these signals are internally
connected to their transmit counterparts, CLKX and FSX.
The bits required to configure the McBSP as an SPI device are introduced in
Table 10. Table 11 shows how the various combinations of the CLKSTP bit and
the polarity bits CLKXP and CLKRP create four possible clock stop mode
configurations. The timing diagrams in section 6.4 show the effects of
CLKSTP, CLKXP, and CLKRP.
SPRU762B