Table of Contents
Advertisement
Table 6.
Input Clock Selection for Sample Rate Generator
3.5
Sample Rate Generator Clocking Examples
3.5.1
Double-Rate ST-Bus Clock
SPRU762B
SCLKME
CLKSM
0
0
1
1
Step 4: If necessary, enable the receiver and/or the transmitter.
If necessary, remove the receiver and/or transmitter from reset by
setting RRST and/or XRST = 1.
Step 5: If necessary, enable the frame-synchronization logic of the sample
rate generator.
After the required data acquisition setup is done (DXR[1/2] is loaded
with data), set GRST = 1 in SPCR2 if an internally generated frame-
synchronization pulse is required. FSG is generated with an active-
high edge after the programmed number of CLKG clocks
(FPER + 1) have elapsed.
This section shows three examples of using the sample rate generator to clock
data during transmission and reception.
Figure 20 shows McBSP configuration to be compatible with the Mitel ST-Bus.
This operation is running at maximum frame frequency.
McBSP Sample Rate Generator
Input Clock for
Sample Rate Generator
0
Signal on CLKS pin
1
CPU clock
0
Signal on CLKR pin
1
Signal on CLKX pin
Multichannel Buffered Serial Ports (McBSPs)
45
Advertisement
Chapters
Table of Contents
