Texas Instruments OMAP5912 Reference Manual page 1671

McBSP Exception/Error Conditions
4.5.3 Preventing Unexpected Transmit Frame-Synchronization Pulses
Figure 33. Proper Positioning of Frame-Synchronization Pulses
60 Multichannel Buffered Serial Ports (McBSPs)
Each frame transfer can be delayed by 0, 1, or 2 CLKX cycles, depending on
the value in the XDATDLY bits of XCR2. For each possible data delay,
Figure 33 shows when a new frame-synchronization pulse on FSX can safely
occur relative to the last bit of the current frame.
For 2-bit delay:
Next frame-synchronization
pulse here or later is OK.
CLKR/CLKX
FSR/FSX
DR/DX
For 1-bit delay:
Next frame-synchronization
pulse here or later is OK.
For 0-bit delay:
Next frame-synchronization
pulse here or later is OK.
Earliest possible
time to begin transfer
of next frame
Last bit of
current frame
SPRU762B