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McBSP Sample Rate Generator
3.3
Synchronizing Sample Rate Generator Outputs to an External Clock
3.3.1
Operating the Transmitter Synchronously with the Receiver
3.3.2
Synchronization Examples
42
Multichannel Buffered Serial Ports (McBSPs)
The sample rate generator can produce a clock signal (CLKG) and a
frame-synchronization signal (FSG) based on an input clock signal that is
either the CPU clock signal or a signal at the CLKS, CLKR, or CLKX pin. When
an external clock is selected to drive the sample rate generator, the GSYNC
bit of SRGR2 and the FSR pin can be used to control the timing of CLKG and
the pulsing of FSG relative to the chosen input clock.
Make GSYNC = 1 when you want the McBSP and an external device to divide
down the input clock with the same phase relationship. If GSYNC = 1:
An
inactive-to-active
-
resynchronization of CLKG and a pulsing of FSG.
CLKG always begins with a high state after synchronization.
-
FSR is always detected at the same edge of the input clock signal that
-
generates CLKG, no matter how long the FSR pulse is.
The FPER bits of SRGR2 are ignored because the frame-synchronization
-
period
on
FSG
frame-synchronization pulse on the FSR pin.
If GSYNC = 0, CLKG runs freely and is not resynchronized, and the
frame-synchronization period on FSG is determined by FPER.
When GSYNC = 1, the transmitter can operate synchronously with the
receiver, provided that:
FSX is programmed to be driven by FSG (FSGM = 1 in SRGR2 and
-
FSXM = 1 in PCR). If the input FSR has appropriate timing so that it can
be sampled by the falling edge of CLKG, it can be used instead, by setting
FSXM = 0 and connecting FSR to FSX externally.
The sample rate generator clock drives the transmit and receive clocking
-
(CLKRM = CLKXM = 1 in PCR). Therefore, the CLK(R/X) pin must not be
driven by any other driving source.
Figure 18 and Figure 19 show the clock and frame-synchronization operation
with various polarities of CLKS (the chosen input clock) and FSR. These
figures assume FWID = 0 in SRGR1, for an FSG pulse that is one CLKG cycle
wide. The FPER bits of SRGR2 are not programmed; the period from the start
of a frame-synchronization pulse to the start of the next pulse is determined
by the arrival of the next inactive-to-active transition on the FSR pin.
transition
on
the
is
determined
by
FSR
pin
triggers
the
arrival
of
the
SPRU762B
a
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