Texas Instruments OMAP5912 Reference Manual page 1650

Figure 17. Possible Inputs to the Sample Rate Generator and the Polarity Bits
Table 5. Polarity Options for the Input to the Sample Rate Generator
Input Clock
Signal on CLKS pin
CPU clock
Signal on CLKR pin
Signal on CLKX pin
3.1.3 Choosing a Frequency for the Output Clock (CLKG)
SPRU762B
CLKX
CLKXP
CLKR
CLKRP
CLKSM
CPU clock
CLKS
CLKSP
Polarity Option
CLKSP = 0 in SRGR2
CLKSP = 1 in SRGR2
Always positive polarity
CLKRP = 0 in PCR
CLKRP = 1 in PCR
CLKXP = 0 in PCR
CLKXP = 1 in PCR
The input clock (CPU clock or external clock) can be divided down by a
programmable value to drive CLKG. Regardless of the source to the sample
rate generator, the rising edge of CLKSRG (see Figure 16) generates CLKG
and FSG.
McBSP Sample Rate Generator
1
0
1
0
Effect
Rising edge on CLKS pin generates transitions on
CLKG and FSG.
Falling edge on CLKS pin generates transitions on
CLKG and FSG.
Rising edge of CPU clock generates transitions on
CLKG and FSG.
Falling edge on CLKR pin generates transitions on
CLKG and FSG.
Rising edge on CLKR pin generates transitions on
CLKG and FSG.
Rising edge on CLKX pin generates transitions on
CLKG and FSG.
Falling edge on CLKX pin generates transitions on
CLKG and FSG.
Multichannel Buffered Serial Ports (McBSPs)
1
CLKSRG
To clock dividers
0
SCLKSME
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