Texas Instruments OMAP5912 Reference Manual page 1659

Multimedia processor device overview and architecture
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McBSP Exception/Error Conditions
McBSP Sample Rate Generator / McBSP Exception/Error Conditions
Figure 22.
Double-Rate Clock Example
CLKS
Internal FS(R/X)
Internal CLK(R/X)
D(R/X)
4
McBSP Exception/Error Conditions
48
Multichannel Buffered Serial Ports (McBSPs)
W32B0
W1B7
W1B6
There are five serial port events that can constitute a system error:
Receiver overrun (RFULL = 1)
-
This occurs when DRR1 has not been read since the last RBR-to-DRR
copy. Consequently, the receiver does not copy a new word from the
RBR(s) to the DRR(s) and the RSR(s) are now full with another new word
shifted in from DR. Therefore, RFULL = 1 indicates an error condition
wherein any new data that can arrive at this time on DR replaces the con-
tents of the RSR(s), and the previous word is lost. The RSRs continue to
be overwritten as long as new data arrives on DR and DRR1 is not read.
For more details about overrun in the receiver, see section 4.1.
Unexpected receive frame-synchronization pulse (RSYNCERR = 1)
-
This occurs during reception when RFIG = 0 and an unexpected frame-
synchronization pulse occurs. An unexpected frame-synchronization
pulse is one that begins the next frame transfer before all the bits of the
current frame have been received. Such a pulse causes data reception to
abort and restart. If new data has been copied into the RBR(s) from the
RSR(s) since the last RBR-to-DRR copy, this new data in the RBR(s) is
lost. This is because no RBR-to-DRR copy occurs; the reception has been
restarted. For more details about receive frame-synchronization errors,
see section 4.2.
Transmitter data overwrite
-
This occurs when the CPU or DMA controller overwrites data in the
DXR(s) before the data is copied to the XSR(s). The overwritten data nev-
er reaches the DX pin. For more details about overwrite in the transmitter,
see section 4.3.
W1B5
W1B4
W1B3
W1B2
W1B1
W1B0
WxBy = word x bit y
SPRU762B
W2B7

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