Table of Contents
Advertisement
McBSP Exception/Error Conditions
4.1.1
Example of Overrun Condition
Figure 23.
Overrun in the McBSP Receiver
CLKR
FSR
Á Á
DR
A1
A0
RRDY
RFULL
4.1.2
Example of Preventing Overrun Condition
50
Multichannel Buffered Serial Ports (McBSPs)
Note:
If both DRRs are needed (word length larger than 16 bits), the CPU or the
DMA controller must read from DRR2 first and then from DRR1. As soon as
DRR1 is read, the next RBR-to-DRR copy is initiated. If DRR2 is not read
first, the data in DRR2 is lost.
After the receiver starts running from reset, a minimum of three words must
be received before RFULL is set. Either of the following events clears the
RFULL bit and allows subsequent transfers to be read properly:
The CPU or DMA controller reads DRR1.
-
The receiver is reset individually (RRST = 0) or as part of an OMAP5912
-
reset.
Another frame-synchronization pulse is required to restart the receiver.
Figure 23 shows the receive overrun condition. Because serial word A is not
read from DRR1 before serial word B arrives in RBR1, B is not transferred to
DRR1 yet. Another new word (C) arrives and RSR1 is full with this data. DRR1
is finally read, but not earlier than 2.5 cycles before the end of word C.
Therefore, new data (D) overwrites word C in RSR1. If DRR1 is not read in
time, the next word can overwrite D.
Á Á Á Á
B7
B6
B5
B4
B3
RBR1 to DRR1 copy(A)
No read from DRR1(A)
Figure 24 shows the case where RFULL is set, but the overrun condition is
prevented by a read from DRR1 at least 2.5 cycles before the next serial word
(C) is completely shifted into RSR1. This ensures that an RBR1-to-DRR1 copy
of word B occurs before receiver attempts to transfer word C from RSR1 to
RBR1.
Á Á
Á Á
B2
B1
B0
C7
C6
No RBR1 to DRR1 copy(B)
Á Á Á Á
C5
C4
C3
C2
C1
C0
No RSR1 to RBR1 copy(C)
No read from DRR1(A)
SPRU762B
D7
Advertisement
Chapters
Table of Contents
