Texas Instruments OMAP5912 Reference Manual page 1677

Multimedia processor device overview and architecture
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Multichannel Selection Modes
Figure 36.
McBSP Data Transfer in the 8-Partition Mode
Eight-partition mode
Partition
Block
Channels
Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á
FS(R/X)
Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á
5.6
Receive Multichannel Selection Mode
66
Multichannel Buffered Serial Ports (McBSPs)
Figure 36 shows an example of the McBSP using the 8-partition mode. In
response to a frame-synchronization pulse, the McBSP begins a frame
transfer with partition A and then activates B, C, D, E, F, G, and H to complete
a 128-word frame.
A
B
C
0
1
2
0−15
16−31
32−47
The RMCM bit of MCR1 determines whether all channels or only selected
channels are enabled for reception. When RMCM = 0, all 128 receive
channels are enabled and cannot be disabled. When RMCM = 1, the receive
multichannel selection mode is enabled. In this mode:
Channels can be individually enabled or disabled. The only channels
-
enabled are those selected in the appropriate receive channel enable
registers (RCERs). The way channels are assigned to the RCERs
depends on the number of receive channel partitions (2 or 8), as defined
by the RMCME bit of MCR1.
If a receive channel is disabled, any bits received in that channel are
-
passed only as far as the receive buffer register(s) (RBR(s)). The receiver
does not copy the content of the RBR(s) to the DRR(s), and as a result,
does not set the receiver ready bit (RRDY). Therefore, no DMA
synchronization event (REVT) is generated and, if the receiver interrupt
mode depends on RRDY (RINTM = 00b), no interrupt is generated.
As an example of how the McBSP behaves in the receive multichannel
selection mode, suppose you enable only channels 0, 15, and 39, and that the
frame length is 40. The McBSP:
1) Accepts bits shifted in from the DR pin in channel 0.
2) Ignores bits received in channels 1-14.
3) Accepts bits shifted in from the DR pin in channel 15.
4) Ignores bits received in channels 16-38.
5) Accepts bits shifted in from the DR pin in channel 39.
D
E
F
3
4
5
48−63
64−79
80−95
G
H
A
6
7
0
96−111
112−127
0−15
SPRU762B

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