Texas Instruments OMAP5912 Reference Manual page 1665

McBSP Exception/Error Conditions
Figure 27. Proper Positioning of Frame-Synchronization Pulses
4.3 Overwrite in the Transmitter
54 Multichannel Buffered Serial Ports (McBSPs)
For 2-bit delay:
Next frame-synchronization
pulse here or later is OK.
CLKR/CLKX
FSR/FSX
DR/DX
As described in section 2.6, the transmitter must copy the data previously
written to the DXR(s) by the CPU or DMA controller into the XSR(s) and then
shift each bit from the XSR(s) to the DX pin. If new data is written to the DXR(s)
before the previous data is copied to the XSR(s), the previous data in the
DXR(s) is overwritten and thus lost.
For 1-bit delay:
Next frame-synchronization
pulse here or later is OK.
For 0-bit delay:
Next frame-synchronization
pulse here or later is OK.
Earliest possible
time to begin transfer
of next frame
Last bit of
current frame
SPRU762B