Texas Instruments OMAP5912 Reference Manual page 1647

Multimedia processor device overview and architecture

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McBSP Sample Rate Generator

Conceptual Block Diagram of the Sample Rate Generator

Multichannel Buffered Serial Ports (McBSPs)

Each McBSP contains a sample rate generator that can be used to generate

an internal data clock (CLKG) and an internal frame-synchronization signal

(FSG). CLKG can be used for bit shifting on the data receive (DR) pin and/or

the data transmit (DX) pin. FSG can be used to initiate frame transfers on DR

and/or DX. Figure 16 is a conceptual block diagram of the sample rate

The source clock for the sample rate generator (labeled CLKSRG in the

diagram) can be supplied by either the 12-MHz DSPXOR_CK clock, the

ARMPER_CK clock, or by an external pin (CLKS, CLKX, or CLKR). The

source is selected with the SCLKME bit of PCR and the CLKSM bit of SRGR2.

If a pin is used, the polarity of the incoming signal can be inverted with the

appropriate polarity bit (CLKSP of SRGR2, CLKXP of PCR, or CLKRP of

synchronization

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