Texas Instruments OMAP5912 Reference Manual page 1635

McBSP Operation
2.2 Companding (Compressing and Expanding) Data
Figure 4. Companding Processes
RSR1
DR
DX
24 Multichannel Buffered Serial Ports (McBSPs)
For transmission, the CPU or the DMA controller must write data to DXR2 first
and then to DXR1. When new data arrives in DXR1, if there is no previous data
in XSR1, the contents of DXR2 and DXR1 are copied to XSR2 and XSR1,
respectively; otherwise, the contents of the DXRs are copied to the XSRs
when the last bit of the previous data is shifted out on the DX pin. After transmit
frame synchronization, the transmitter begins shifting bits from the XSRs to the
DX pin. For more details about transmission, see section 2.6.
Companding (COMpressing and exPANDing) hardware allows compression
and expansion of data in either µ-law or A-law format. The companding
standard employed in the United States and Japan is µ-law. The European
companding standard is referred to as A-law. The specifications for µ-law and
A-law log PCM are part of the CCITT G.711 recommendation.
A-law and µ-law allow 13 bits and 14 bits of dynamic range, respectively. Any
values outside this range are set to the most positive or most negative value.
Thus, for companding to work best, the data transferred to and from the
McBSP via the CPU or DMA controller must be at least 16 bits wide.
The µ-law and A-law formats both encode data into 8-bit code words.
Companded data is always 8 bits wide; the appropriate word length bits
(RWDLEN1, RWDLEN2, XWDLEN1, XWDLEN2) must therefore be set to 0,
indicating an 8-bit wide serial data stream. If companding is enabled and either
of the frame phases does not have an 8-bit word length, companding
continues as if the word length is 8 bits.
Figure 4 illustrates the companding processes. When companding is chosen
for the transmitter, compression occurs during the process of copying data
from DXR1 to XSR1. The transmit data is encoded according to the specified
companding law (A-law or µ-law). When companding is chosen for the
receiver, expansion occurs during the process of copying data from RBR1 to
DRR1. The receive data is decoded to twos-complement format.
8
RBR1
Expand
8
Compress
XSR1
16
DRR1
To CPU or DMA controller
16
DXR1
From CPU or DMA controller
SPRU762B