STMicroelectronics SPC572L series Reference Manual page 2029

RM0400
Date
03-Apr-2013
Table 1150. Revision history(Continued)
Rev
Table 15: Reset settings for e200z215An3
– Removed one instance of footnote "Reset by processor reset...
unconditionally by POR" (previously listed twice)
– Removed rows "L1CFG0", "L1CFG1", "L1CSR0, 1" and "L1FINV0, 1"
Table 18: Crossbar switch master
– Changed master module description for Port 0 to "Core data bus" (was
core instruction bus)
– Changed master module description for Port 1 to "Core instruction bus"
(was core data bus)
Section 6.3.5, Platform Configuration Module
and content relating to FEC BURST Optimization Control Register
(FBOMCR) and IAHB Burst Enable 1(IAHB_BE1) register
Table 23: Interrupt
– Changed Source Descriptions and Source names from "IRQ#837" to
"IRQ#848"
– Updated source description and source name for IRQ 484 (was
ipi_int_ext_pd1_done / ipi_int_ext_pd1_done; is PLL_0_1 /
PLL0SR[EXTPDF])
Table 33 (ERM memory assignment): updated "Assigned memory"
descriptions for rows "Memory0, Memory4 and Memory5"
Table 34 (EIM memory assignment): updated "Assigned memory"
descriptions for rows "Memory4 and Memory5"
Section 6.6, Timers: changed number of generic 32-bit timer channels for
2
PIT module to four (was eight)
(cont'd)
Table 36:
"GTM101 Generic Timer Module"
Updated introduction of
Table 41: PIT0 memory
(was [0:7])
Removed section "Fast Ethernet Controller (FEC) configuration"
Section 6.7.1, FEC
updated content.
Removed section CAN subsystem configuration
Section 6.7.3.2, Device specific
"0AF0201Dh0AF02041h" was "0AF0601Dh0AF06041h"
Added Section 6.7.4, DSPI configuration
Figure 24 (DSPI Module Configuration Register
– Changed bit 16 to reserved
– Changed bit 28 to "XSPI"
Added Table 48: DSPIx_MCR field descriptions
Added Section 6.7.7, LINFlexD implemented registers
Section 6.7.12.2, Clock Monitor Unit (CMUIOP) protected
renamed (was I/O Processor Clock Monitor Unit (CMUIOP) protected
registers)
Table 50: LINFlexD
linflex_1 and linflex_14 from '16' to '0'
Section 6.3.8.1, DMA channel assignment: updated number of multiplexers
to 2 (was 4)
DocID027809 Rev 4
Changes
sources:
Timers: changed "GTM101 Integration Module Configuration" to
Section 6.7.2.3, Default configuration
map: changed range of Timer Channels to [0:3]
interface: renamed (was FEC interface selection);
features: changed SIPI CHIP ID to
configurations: changed the number of filters for
Revision history
resources:
assignments:
(PCM): Removed references
(DSPIx_MCR)):
registers:
2029/2058
2057