STMicroelectronics SPC572L series Reference Manual page 2037

RM0400
Date
03-Apr-2013
Table 1150. Revision history(Continued)
Rev
34: Analog-to-digital converter (ADC) configuration
Section 34.1, ADC
Delta ADCs share the same supply pins
(VDD_HV_ADV/VSS_HV_ADV) and ground, but have separate
reference pins" to "All SAR and Sigma-Delta ADCs share the same
supply pins (VDD_HV_ADV/VSS_HV_ADV), ground, as well as
reference pins."
Table 280: Sigma-Delta ADC external signal
VDD_HV_ADR signal voltage value to "3–5 V" (was 5 V)
Table 286: SARB analog test channel
SAR" and "Fast SAR Channel"
Chapter 39: Sigma-Delta Analog-to-Digital Converter (SDADC) Digital
Interface
Section 39.3,
"Signed/unsigned format of converted data output"
Table 357 (MCR field descriptions): updated description of field "GECEN"
Section 39.6.2.5, Request Select and Enable Register
description of field "CDVEE"
Section 39.6.2.7, FIFO Control Register
– Added the FOWEN control bit to enable the overwrite option for FIFO
– Added FRST reset bit to provide option for FIFO flush
Section 39.7.11, Gain calibration
– Updated steps 7, 10, 11, 12, and note "The gain error calibration should
2
only be done"
(cont'd)
– Added two notes: "MCR[GECEN] = 1 ensures the accurate gain error..."
and "The higher the number of full-scale conversion..."
Section 39.7.12, Offset calibration
Section 39.8, Initialization
filter is required." to "Enable high-pass filter if required."
Added Section 39.8.1, Data conversion step
Chapter 36, Successive Approximation Register Analog-to-Digital
Converter (SARADC) Digital Interface:
Section 1.2,
Added sentence "The number of input channels and their mapping..." to
note "See the device-specific Analog-to-Digital Converters (ADC)..."
Moved note "SARB implements a bias generator..." to
block diagram)
Figure 1 (SARADC block
"Vssm" to "VSS_HV_ADV", "VAREF1" to "VDD_HV_ADR", and
"VAGND1" to "VSS_HV_ADR"
Updated Section 36.4.1.1, Start of normal conversion
Section 1.4.2, Injected channel
item of bulleted list; added details about Enqueuing feature.
Section 1.4.10,
conversion should not be ... bits (ECNCMR or ECJCMR) are set."
Section 1.5.1.3, Interrupt Status Register
Added note to
channel
DocID027809 Rev 4
Changes
overview: changed paragraph "All SAR and Sigma-
Features: removed items "Left/right data alignment" and
support:
support: updated step 2
information: changed item "Enable high-pass
Overview:
diagram): changed "Vddm" to "VDD_HV_ADV",
conversion: updated "By injection trigger"
Interrupts: added sentence "It is recommended that
Section 1.4.6, Test channel connection with internal analog
Revision history
description: changed
assignment: removed columns "Fast
(RSER): updated
(FCR):
Figure 1 (SARADC
(ISR): Added CTUTRGERR field
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