STMicroelectronics SPC572L series Reference Manual page 2031

RM0400
Date
03-Apr-2013
Table 1150. Revision history(Continued)
Rev
Chapter 11: Security
Section 11.1, Basic
part..." from security features list
11: Calibration and Debug
Table 112: DCF client
– Added OTP section with 4 corresponding OTP_ENx registers
– Set UTEST Miscellaneous reset value to 0x00000941
Section 11.2.1, Debug and Calibration Interface
sharing logic..."
Removed section "Compact JTAG (CJTAG)"
Table 82: DCI_PINCR register field
"reserved"
Section 11.2.3.1, SPU Level1 input Mux configurations
26 MUX inputs MUX 22 [110]–MUX 24 [110], MUX 34 [110], MUX 35 [110],
MUX 36 [000], MUX 37 [100], MUX 37 [000], MUX 38 [000], MUX 38 [010],
MUX 39 [000], MUX 48 [011]–MUX 55 [011], MUX 56 [010]– MUX 62 [010]
Table 85: L1SEL2 register field
MUX 20 [110] and MUX 21 [110]
Table 87: L1SEL4 register field
MUX 34 [110], MUX 35 [110], MUX 36 [000]–MUX 38 [000],
MUX 38 [010], and MUX 39 [000]
Section 11.5.2, Nexus Aurora Router
changed to 0x0D001FFF
2
12: Core e200z215An3
(cont'd)
Chapter 16: System Integration Unit Lite2 (SIUL2)
Updated SIUL2 MSCR names to I/O Pin Multiplexed Signal Configuration
Registers (SIUL2_MSCR_IO_0–SIUL2_MSCR_IO_511) and
Multiplexed Signal Configuration Registers for Multiplexed Input
Selection (SIUL2_MSCR_MUX_512–SIUL2_MSCR_MUX_1023)
Section 16.1.2,
– Updated number of GPIO ports (is 7, was 1 to 32)
– Updated number of interrupt sources (is 3, was 1 to 32)
Table 199: SIUL2 memory
changed to 0x00BC; 0x0240–0x123F end address changed to 0x123C;
row "SUIL2 User Defined Register 0–User Defined Register 63
(SIUL2_UDR0–SIUL2_UDR63)" changed to Reserved
Table 200: SIUL2_MIDR1 field
"PKG"
Table 201: SIUL2_MIDR2 field
"FAMILYNUM"
Section 16.2.2.3, SIUL2 DMA/Interrupt Status Flag Register 0
(SIUL2_DISR0): added fields relative to bits 28–30
Section 16.2.2.4, SIUL2 DMA/Interrupt Request Enable Register 0
(SIUL2_DIRER0): added fields relative to bits 28–30
Section 16.2.2.5, SIUL2 DMA/Interrupt Request Select Register 0
(SIUL2_DIRSR0): added fields relative to bits 28–30
Section 16.2.2.6, SIUL2 Interrupt Rising-Edge Event Enable Register 0
(SIUL2_IREER0): added fields relative to bits 28–30
DocID027809 Rev 4
Changes
security: removed "BAR software routines to initialize
list:
descriptions: bits 3–6 and 11–15 set to
descriptions: removed MUX inputs
descriptions: removed MUX inputs
(NAR): end address for overlay RAM
description: no substantial changes
Features:
map: row 0x0040–0x00BF end address
descriptions: updated description of field
description: updated description of field
Revision history
(DCI): removed "Port
registers: removed
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