STMicroelectronics SPC572L series Reference Manual page 2035

RM0400
Date
03-Apr-2013
Table 1150. Revision history(Continued)
Rev
Section 24.3.1.26, Auxiliary Clock 7 Select Status Register
(CGM_AC7_SS): update address value from 0x08E0 to 0x08E4
Deleted "MC_CGM memory map" table
Table 225: MC_CGM register
Section 24.3.1.8, PCS Divider Change Register 3 (CGM_PCS_DIVC3)
Section 24.3.1.10, PCS Divider End Register 3
changed "reserved" to "PLL0 PHI1"
Figure 204 (PCS Divider Change Register 3
corrected address
Figure 205 (PCS Divider Start Register 3
address
Figure 206 (PCS Divider End Register 3
address
Chapter 27: Fast OSC Digital Interface (FXOSC)
Table 322: XOSC
XOSC_CTL[OSCBYP]
Section 27.2.4, Oscillator bypass
must be running before..."
Table 324: FXOSC_CTL register field
– Removed footnote "Software can read as well as set the OSCBYP bit."
– Removed redundant table footnote "Software can read as well as clear
the I_OSC bit." from OSCBYP field of CTL register
Added note in
Section 27.3.1.1, FXOSC control register
2
– updated reset value for M_OSC to '1'
(cont'd)
– updated reset value for M_OSC to '–' and added note referring to the
"Clocking" chapter
Chapter 26, IRCOSC digital interface
Added new topic heading,
Updated Section 31.2, Functional
27: RAM controller
Section 27.2, Memory map and register
controller memory map and register definition")
Updated Table 234: RAM controller memory map
Table 235: Platform RAM Configuration Register 1 field
renamed (was "Platform RAM Configuration Register 1 description")
Chapter 28, Flash memory controller (PFLASH Controller)
Section 28.4, Memory map and register definitions: renamed (was Flash
memory controller memory map)
Table 4: PFCR1 field
– Changed descriptions for fields P0_BFEN and P1_BFEN
– Removed wait-state data from RWSC field description
– Removed reference to "Port 1" from RWSC field descriptions
Figure 7 (Platform Flash Configuration Register 3 (PFCR3)):
– Added register offset and access information
– Bit 17 read value changed to '0' (was undefined)
– Removed references to Port 1 from BAF_DIS field description.
DocID027809 Rev 4
Changes
description: updated address column
configurations: upated CTL[OSCBYP] to
mode: added note "The external oscillator
descriptions:
Section 27.3.1, Register descriptions
Section 31.1, Introduction
description:
(PRAM):
descriptions:
Revision history
(CGM_PCS_DIVE3):
(CGM_PCS_DIVC3)):
(CGM_PCS_DIVS3)): corrected
(CGM_PCS_DIVE3)): corrected
(FXOSC_CTL):
definition: renamed (was "SRAM
descriptions:
to
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