Table of Contents
Advertisement
MRC p15, 0, <Rd>, c15, c9, 0
MCR p15, 0, <Rd>, c15, c9, 0
3.2.51
c15, Performance Monitor Control Register
ARM DDI 0301H
ID012310
Table 3-135 lists the results of attempted access for each mode.
Table 3-135 Results of access to the Secure User and Non-secure Access
Secure Privileged
Read
Data
To access the Secure User and Non-secure Access Validation Control Register read or write
CP15 with:
•
Opcode_1 set to 0
•
CRn set to c15
•
CRm set to c9
•
Opcode_2 set to 0.
For example:
; Read Secure User and Non-secure Access Validation Control Register
; Write Secure User and Non-secure Access Validation Control Register
The purpose of the Performance Monitor Control Register is to control the operation of:
•
the Cycle Counter Register
•
the Count Register 0
•
the Count Register 1.
Table 3-136 on page 3-134 lists the purpose of the individual bits in the register.
The Performance Monitor Control Register is:
•
in CP15 c15
•
a 32-bit read/write register common to Secure and Non-secure worlds
•
accessible in User and Privileged modes.
Figure 3-73 shows the bit arrangement for the Performance Monitor Control Register.
31
28 27
SBZ/UNP
EvtCount0
Copyright © 2004-2009 ARM Limited. All rights reserved.
Non-Confidential, Unrestricted Access
Non-secure Privileged
Write
Data
Undefined exception
20 19
12 11
EvtCount1
Figure 3-73 Performance Monitor Control Register format
System Control Coprocessor
Validation Control Register
User
Undefined exception
10
9
8
7 6
5
4 3 2 1 0
E
E
E
C
C
C
S
X
C
R
R
B
C
C
C
D
C P
C
1
0
R
1
0
Z
E
3-133
Hide quick links:
Advertisement
Table of Contents
