Table 3-7 Results Of Access To The Cache Type Register; Table 3-8 Example Cache Type Register Format - ARM ARM1176JZF-S Technical Reference Manual

ARM DDI 0301H
ID012310
Table 3-7 lists the results of attempted access for each mode.
Secure Privileged
Read Write
Data Undefined exception
To use the Cache Type Register read CP15 with:
• Opcode_1 set to 0
• CRn set to c0
• CRm set to c0
• Opcode_2 set to 1.
For example:
MRC p15,0,<Rd>,c0,c0,1; returns cache details
Table 3-8, for example, lists the Cache Type Register values for an ARM1176JZF-S processor
with:
• separate instruction and data caches
• cache size = 16KB
• associativity = 4-way
• line length = eight words
• caches use write-back, CP15 c7 for cache cleaning, and Format C for cache lockdown.
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Table 3-7 Results of access to the Cache Type Register

Non-secure Privileged
Read Write
Data Undefined exception

Table 3-8 Example Cache Type Register format

Bits Field name
[31:29] Reserved
[28:25] Ctype
[24] S
[23] Dsize P
[22] Reserved
[21:18] Size
[17:15] Assoc
[14] M
[13:12] Len
[11] Isize P
[10] Reserved
[9:6] Size
[5:3] Assoc
[2] M
[1:0] Len
System Control Coprocessor
User
Undefined exception
Value Behavior
b000
b1110
b1 Harvard cache
b0
b0
b0101 16KB
b010 4-way
b0
b10 8 words per line, 32 bytes
b0
b0
b0101 16KB
b010 4-way
b0
b10 8 words per line, 32 bytes
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