Table 3-127 Fcse Pid Register Bit Functions; Table 3-128 Results Of Access To The Fcse Pid Register; Figure 3-68 Fcse Pid Register Format - ARM ARM1176JZF-S Technical Reference Manual

3.2.46 c13, FCSE PID Register
Bits Field name
[31:25] FCSE PID
[24:0] -
ARM DDI 0301H
ID012310
The c13, Context ID Register on page 3-128 replaces the FCSE PID Register. Use of the FCSE
PID Register is deprecated.
The FCSE PID Register is:
• in CP15 c13
• a 32-bit read/write register banked for Secure and Non-secure worlds
• accessible in privileged modes only.
Writing to this register globally flushes the BTAC.
Figure 3-68 shows the arrangement of bits in the register.
31 25 24
FCSE PID
Table 3-127 lists how the bit values correspond with the FCSE PID Register functions.
Function
The purpose of the FCSE PID Register is to provide the ProcID for fast context switch memory
mappings. The MMU uses the contents of this register to map memory addresses in the range
0-32MB.
Identifies a specific process for fast context switch.
Holds the ProcID. The reset value is 0.
Reserved.
SBZ.
Attempts to write to this register in Secure Privileged mode when CP15SDISABLE is HIGH
result in an Undefined exception, see TrustZone write access disable on page 2-9.
Table 3-128 lists the results of attempted access for each mode.
Secure Privileged
Read Write
Secure data Secure data
To use the FCSE PID Register read or write CP15 with:
• Opcode_1 set to 0
• CRn set to c13
• CRm set to c0
• Opcode_2 set to 0.
For example:
MRC p15, 0, <Rd>, c13, c0, 0
MCR p15, 0, <Rd>, c13, c0, 0
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SBZ

Figure 3-68 FCSE PID Register format

Table 3-127 FCSE PID Register bit functions

Table 3-128 Results of access to the FCSE PID Register

Non-secure Privileged
Read Write
Non-secure data Non-secure data
; Read FCSE PID Register
; Write FCSE PID Register
System Control Coprocessor
0
User
Undefined exception
3-126