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8.8
Locked access
ARM DDI 0301H
ID012310
The AXI protocol specifies that, when a locked transaction occurs, the master must follow the
locked transaction with an unlocked transaction to remove the lock of the interconnect. For
ARM1176JZF-S processors, this implies that, in the case of an abort received on the read part
of a SWP instruction, the Peripheral port or Data port issues a dummy write access with all byte
strobes LOW at the same address as the read access and with AWLOCK = 00, normal
transaction.
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Level Two Interface
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