ARM ARM1176JZF-S Technical Reference Manual page 126

ARM DDI 0301H
ID012310
If high vectors configured then
PC = 0xFFFF0004
else
PC = Non_Secure_Base_Address + 0x00000004
else
R14_mon = address of the next instruction after the SMC instruction
SPSR_mon = CPSR
CPSR [4:0] = 0b10110 /* Enter Secure Monitor mode */
CPSR [5] = 0 /* Execute in ARM state */
CPSR [6] = 1 /* Disable fast interrupts */
CPSR [7] = 1 /* Disable interrupts */
CPSR [8] = 1 /* Disable imprecise aborts */
CPSR [9] = Secure EE-bit /* store value of secure Ctrl Reg bit[25] */
CPSR[24] = 0 /* Clear J bit */
PC = Monitor_Base_Address + 0x00000008
Exceptions occurring in Secure world
The behavior in Secure state is identical to that in Non-secure state, except that
Secure_Base_Address is used instead of Non_Secure_Base_Address and that CPSR[6], F bit,
and CPSR[8], A bit, are updated regardless the bits [5:4] of the Secure Configuration Register.
Except Reset, the software model does not expect any other exception to occur in Secure
Monitor mode. However, if an exception occurs in Secure Monitor mode, the NS bit in SCR
register is automatically reset and the core branches either to the exception handler in Secure
world or in Secure Monitor mode, Secure Monitor mode for IRQ, FIQ or external aborts with
the corresponding bit set in SCR[3:1].
The following exceptions occur in the Secure world:
• Reset
• Undefined instruction on page 2-54
• Software Interrupt exception on page 2-54
• External Prefetch Abort on page 2-54
• Internal Prefetch Abort on page 2-55
• External Data Abort on page 2-50
• Internal Data Abort on page 2-55
• Interrupt request (IRQ) exception on page 2-56
• Fast Interrupt Request (FIQ) exception on page 2-56
• Secure Monitor Call Exception on page 2-57.
Reset
When Reset is de-asserted:
/* Stay in secure state */
R14_svc = UNPREDICTABLE value
SPSR_svc = UNPREDICTABLE value
CPSR [4:0] = 0b10011 /* Enter supervisor mode */
CPSR [5] = 0 /* Execute in ARM state */
CPSR [6] = 1 /* Disable fast interrupts */
CPSR [7] = 1 /* Disable interrupts */
CPSR [8] = 1 /* Disable imprecise aborts */
CPSR [9] = Secure EE-bit /* store value of Secure Control Register bit[25] */
CPSR[24] = 0 /* Clear J bit */
if high vectors configured then
PC = 0xFFFF0000
else
PC = 0x00000000
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/* SMC vectored to the */
/*conventional SVC vector */
Programmer's Model
2-53