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11.4
Token queues
11.4.1
Instruction queue
ARM DDI 0301H
ID012310
The following sections describe each of the synchronizing queues:
•
Instruction queue
•
Length queue on page 11-13
•
Accept queue on page 11-13
•
Cancel queue on page 11-14
•
Finish queue on page 11-14.
The core passes every instruction fetched from memory across the coprocessor interface, where
it enters the instruction queue. Ideally it only passes on the coprocessor instructions, but has not,
at this stage, had time to decode the instruction.
The coprocessor decodes the instruction on arrival in its own Decode stage and rejects the
non-coprocessor instructions. The core does not require any acknowledgement of the removal
of these instructions because each instruction type is determined within the coprocessors
Decode stage. This means that the instruction received from the core must be decoded as soon
as it enters the instruction queue. The instruction queue is a modified version of the standard
queue, that incorporates an instruction decoder. Figure 11-7 shows an instruction queue
implementation.
The decoder decodes the instruction written into buffer A as soon as it arrives. The subsequent
buffers, B and C, receive the decoded version of the instruction in buffer A.
The A flag now indicates that the data in buffer A are valid and represent a coprocessor
instruction. This means that non-coprocessor or unrecognized instructions are immediately
dropped from the instruction queue and are never passed on.
The coprocessor must also compare the coprocessor number field in a coprocessor instruction
and compare it with its own number, given by ACPNUM. If the number does not match, the
instruction is invalid. The instruction queue provides an interface to the core through the
following signals, that the core drives:
ACPINSTRV
This signal is asserted when valid data are available from the core. It must
be clocked directly into the buffer A flag, unless the queue is full, when
case it is ignored.
ACPINSTR[31:0] This is the instruction being passed to the coprocessor from the core, and
must be clocked into buffer A.
ACPINSTRT[3:0] This is the flush tag associated with the instruction in ACPINSTR, and
must be clocked into the tag associated with buffer A.
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Coprocessor Interface
V
Output
Interconnect
S0
Buffer A
A
Decoder
0
B
Buffer B
1
0
C
Buffer C
1
Figure 11-7 Instruction queue
S1
Out
11-12
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