Table 15-3 Etmiasecctl[1:0]; Table 15-4 Data Address Interface Signals - ARM ARM1176JZF-S Technical Reference Manual

15.1.2 Secure control bus
15.1.3 Data address interface
ARM DDI 0301H
ID012310
In these cases, if an exception occurs before the first instruction is traced, an additional
placeholder instruction is traced. The placeholder instruction is followed immediately by a
branch packet that indicates the type of exception. This exception is marked as a canceling
exception, to indicate that the placeholder instruction was not executed. The instruction at the
exception vector is then traced, and trace continues as normal.
This extra instruction cannot be generated on a reset exception. Therefore, if the processor exits
Debug state or a prohibited region because of a reset, trace does not report a reset exception.
For more information on the ETM protocol, see the Embedded Trace Macrocell Architecture
Specification.
The Secure control bus ETMIASECCTL indicates when the processor is in Secure state and
when the data trace is prohibited.
Table 15-3 lists the signals in the Secure control bus ETMIASECCTL.
Bits Reference name
IASProhibited
[1]
IASNonSecure
[0]
Data addresses are sampled at the ADD stage because they are guaranteed to be in order at this
point. These are assigned a slot number for identification on retirement.
Table 15-4 lists the data address interface signals.
Signal name
ETMDACTL[17:0
]
ETMDA[31:3]
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Description
Trace prohibited for this instruction
Instruction executed in Non-secure state

Table 15-4 Data address interface signals

Description
Data address interface control signals
Address for data transfer
Trace Interface Port

Table 15-3 ETMIASECCTL[1:0]

Qualified by
IAValid
IAValid
Qualified by
-
DASlot != 00 AND !DACPRT
15-4