ARM ARM1176JZF-S Technical Reference Manual page 11

Table 3-65 Results of access to the Fault Address Register ...................................................................... 3-68
Table 3-66 Results of access to the Instruction Fault Address Register ..................................................... 3-69
Table 3-67 Functional bits of c7 for Set and Index ...................................................................................... 3-72
Table 3-68 Cache size and S parameter dependency ................................................................................ 3-72
Table 3-69 Functional bits of c7 for MVA .................................................................................................... 3-73
Table 3-70 Functional bits of c7 for VA format ............................................................................................ 3-74
Table 3-71 Cache operations for entire cache ............................................................................................ 3-74
Table 3-72 Cache operations for single lines .............................................................................................. 3-75
Table 3-73 Cache operations for address ranges ....................................................................................... 3-76
Table 3-74 Cache Dirty Status Register bit functions ................................................................................. 3-78
Table 3-75 Cache operations flush functions .............................................................................................. 3-79
Table 3-76 Flush Branch Target Entry using MVA bit functions ................................................................. 3-79
Table 3-77 PA Register for successful translation bit functions .................................................................. 3-80
Table 3-78 PA Register for unsuccessful translation bit functions .............................................................. 3-81
Table 3-79 Results of access to the Data Synchronization Barrier operation ............................................. 3-84
Table 3-80 Results of access to the Data Memory Barrier operation ......................................................... 3-85
Table 3-81 Results of access to the Wait For Interrupt operation ............................................................... 3-85
Table 3-82 Results of access to the TLB Operations Register ................................................................... 3-86
Table 3-83 Instruction and data cache lockdown register bit functions ....................................................... 3-88
Table 3-84 Results of access to the Instruction and Data Cache Lockdown Register ................................ 3-88
Table 3-85 Data TCM Region Register bit functions ................................................................................... 3-90
Table 3-86 Results of access to the Data TCM Region Register ................................................................ 3-91
Table 3-87 Instruction TCM Region Register bit functions .......................................................................... 3-92
Table 3-88 Results of access to the Instruction TCM Region Register ....................................................... 3-93
Table 3-89 Data TCM Non-secure Control Access Register bit functions .................................................. 3-94
Table 3-90 Effects of NS items for data TCM operation ............................................................................. 3-94
Table 3-91 Instruction TCM Non-secure Control Access Register bit functions ......................................... 3-95
Table 3-92 Effects of NS items for instruction TCM operation .................................................................... 3-95
Table 3-93 TCM Selection Register bit functions ........................................................................................ 3-96
Table 3-94 Results of access to the TCM Selection Register ..................................................................... 3-97
Table 3-95 Cache Behavior Override Register bit functions ....................................................................... 3-98
Table 3-96 Results of access to the Cache Behavior Override Register .................................................... 3-98
Table 3-97 TLB Lockdown Register bit functions ...................................................................................... 3-100
Table 3-98 Results of access to the TLB Lockdown Register ................................................................... 3-100
Table 3-99 Primary Region Remap Register bit functions ........................................................................ 3-102
Table 3-100 Encoding for the remapping of the primary memory type ....................................................... 3-103
Table 3-101 Normal Memory Remap Register bit functions ....................................................................... 3-103
Table 3-102 Remap encoding for Inner or Outer cacheable attributes ....................................................... 3-104
Table 3-103 Results of access to the memory region remap registers ....................................................... 3-104
Table 3-104 DMA identification and status register bit functions ................................................................ 3-106
Table 3-105 DMA Identification and Status Register functions ................................................................... 3-106
Table 3-106 Results of access to the DMA identification and status registers ........................................... 3-107
Table 3-107 DMA User Accessibility Register bit functions ........................................................................ 3-108
Table 3-108 Results of access to the DMA User Accessibility Register ..................................................... 3-108
Table 3-109 DMA Channel Number Register bit functions ......................................................................... 3-109
Table 3-110 Results of access to the DMA Channel Number Register ...................................................... 3-109
Table 3-111 Results of access to the DMA enable registers ...................................................................... 3-111
Table 3-112 DMA Control Register bit functions ......................................................................................... 3-112
Table 3-113 Results of access to the DMA Control Register ...................................................................... 3-113
Table 3-114 Results of access to the DMA Internal Start Address Register ............................................... 3-114
Table 3-115 Results of access to the DMA External Start Address Register ............................................. 3-115
Table 3-116 Results of access to the DMA Internal End Address Register ................................................ 3-116
Table 3-117 DMA Channel Status Register bit functions ............................................................................ 3-117
Table 3-118 Results of access to the DMA Channel Status Register ......................................................... 3-119
Table 3-119 DMA Context ID Register bit functions ................................................................................... 3-120
Table 3-120 Results of access to the DMA Context ID Register ................................................................ 3-120
Table 3-121 Secure or Non-secure Vector Base Address Register bit functions ....................................... 3-121
Table 3-122 Results of access to the Secure or Non-secure Vector Base Address Register .................... 3-122
Table 3-123 Monitor Vector Base Address Register bit functions ............................................................... 3-123
Table 3-124 Results of access to the Monitor Vector Base Address Register ............................................ 3-123
ARM DDI 0301H
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