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6.7.3 Strongly Ordered memory attribute
6.7.4 Ordering requirements for memory accesses
ARM DDI 0301H
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Barrier memory barrier. For non-shared device memory, the data of a write is visible to the
processor before the end of a Data Synchronization Barrier memory barrier. See Explicit
Memory Barriers on page 6-25.
Another memory attribute, Strongly Ordered, is defined on a per-page basis in the MMU.
Accesses to memory marked as Strongly Ordered have a strong memory-ordering model with
respect to all explicit memory accesses from that processor. An access to memory marked as
Strongly Ordered acts as a memory barrier to all other explicit accesses from that processor,
until the point at which the access is complete.
That is, has changed the state of the target location or data has been returned. In addition, an
access to memory marked as Strongly Ordered must complete before the end of a Memory
Barrier. See Explicit Memory Barriers on page 6-25. To maintain backwards compatibility with
ARMv5 architecture, any ARMv5 instructions that implicitly or explicitly change the interrupt
masks in the CSPR that appear in program order after a Strongly Ordered access must wait for
the Strongly Ordered memory access to complete.
These instructions are MSR with the control field mask bit set, and the flag setting variants of
arithmetic and logical instructions whose destination register is R15, that copies the SPSR to
CSPR. This requirement exists only for backwards compatibility with previous versions of the
ARM architecture, and the behavior is deprecated in ARMv6. Programs must not rely on this
behavior, but instead include an explicit Memory Barrier between the memory access and the
following instruction. See Explicit Memory Barriers on page 6-25.
The processor does not require an explicit memory barrier in this situation, but for future
compatibility it is recommended that programmers insert a memory barrier.
Explicit accesses from the processor to memory marked as Strongly Ordered occur at their
program size, and the number of accesses that occur to such locations is the number that are
specified by the program. Implementations must not repeat accesses to such locations when
there is only one access in the program. That is, the accesses are not restartable.
If a memory operation that causes multiple transactions, such as LDM or an unaligned memory
access, crosses a 4KB address boundary, then it might perform more accesses than are specified
by the program regardless of one or both of the areas being marked as Strongly Ordered.
For this reason, it is important that accesses to volatile memory devices are not made using
single instructions that cross a 4KB address boundary. Address locations marked as Strongly
Ordered are not held in a cache, and are treated as Shared memory locations. For Strongly
Ordered memory, the data and side effects of a write are visible to all observers before the end
of a Data Synchronization Barrier memory barrier. See Explicit Memory Barriers on page 6-25.
The various memory types defined in this section have restrictions in the memory orderings that
are permitted.
Ordering requirements for two accesses
The order of any two explicit architectural memory accesses where one or more are to memory
marked as Non-Shared must obey the ordering requirements that Figure 6-1 on page 6-24 lists.
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