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3.2.5
c0, TLB Type Register
Bits
Field name
[31:24]
-
[23:16]
ILsize
[15:8]
DLsize
[7:1]
-
[0]
U
ARM DDI 0301H
ID012310
For example:
MRC p15,0,<Rd>,c0,c0,2
The purpose of the TLB Type Register is to return the number of lockable entries for the TLB.
The TLB has 64 entries organized as a unified two-way set associative TLB. In addition, it has
eight lockable entries that the read-only TLB Type Register specifies.
The TLB Type Register is:
•
in CP15 c0
•
a 32-bit read only register common to the Secure and Non-secure worlds
•
accessible in privileged modes only.
Figure 3-13 shows the bit arrangement for the TLB Type Register.
31
24 23
SBZ/UNP
Table 3-10 lists how the bit values correspond with the TLB Type Register functions.
Function
UNP/SBZ
Instruction lockable size specifies the number of instruction TLB lockable entries
0, indicates that the ARM1176JZF-S processor has a unified TLB
Data lockable size specifies the number of unified or data TLB lockable entries
0x08
, indicates the ARM1176JZF-S processors has 8 unified TLB lockable entries
UNP/SBZ
Unified specifies if the TLB is unified, 0, or if there are separate instruction and data TLBs, 1.
0, indicates that the ARM1176JZF-S processor has a unified TLB
Table 3-11 lists the results of attempted access for each mode.
Secure Privileged
Read
Write
Data
Undefined exception
To use the TLB Type Register read CP15 with:
•
Opcode_1 set to 0
•
CRn set to c0
•
CRm set to c0
•
Opcode_2 set to 3.
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; returns TCM status register
16 15
ILsize
Table 3-10 TLB Type Register bit functions
Table 3-11 Results of access to the TLB Type Register
Non-secure Privileged
Read
Write
Data
Undefined exception
System Control Coprocessor
8 7
DLsize
SBZ/UNP
Figure 3-13 TLB Type Register format
User
Undefined exception
1 0
U
3-25
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