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14.8.2
General setup
14.8.3
Forcing the processor to halt
14.8.4
Entering Debug state
ARM DDI 0301H
ID012310
RTI
1.
Go through Run-Test/Idle DBGTAPSM state. This forces the execution of the instruction
currently loaded into the ITR, provided the execute ARM instruction enable bit,
DSCR[13], is set, the Ready flag was captured as set, and the sticky precise Data Abort
flag is cleared.
You must setup the following control bits before DBGTAP debugging can take place:
•
DSCR[14] Debug-mode select bit must be set to 1.
•
DSCR[6] sticky precise Data Abort flag must be cleared down, so that aborts are not
detected incorrectly immediately after startup.
The DSCR must be read, the DSCR[14] bit set, and the new value written back. The action of
reading the DSCR automatically clears the DSCR[6] sticky precise Data Abort flag. All
individual breakpoints, watchpoints, and vector catches reset disabled on power-up.
Scan the Halt instruction into the DBGTAP controller IR and go through Run-Test/Idle.
To enter Debug state you must:
1.
Check whether the core has entered Debug state, as follows:
SCAN_N 1
INTEST
LOOP
DATAOUT readDSCR
UNTIL
readDSCR[0]==1
2.
Save DSCR, as follows:
DATAOUT readDSCR
Save value in readDSCR
3.
Save wDTR, in case it contains some data, as follows:
SCAN_N 5
INTEST
DATA
0x00000000 Valid wDTR
If Valid==1 then Save value in wDTR
4.
Set the DSCR[13] execute ARM instruction enable bit, so instructions can be issued to the
core from now:
SCAN_N 1
EXTEST
DATA modifiedDSCR
5.
Before executing any instruction in Debug state you have to drain the write buffer. This
ensures that no imprecise Data Aborts can return at a later point:
SCAN_N 4
INST
MCR p15,0,Rd,c7,c10,4
LOOP
LOOP
SCAN_N 4
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; select DSCR
; until Core Halted bit is set
; select DTR
; select DSCR
; modifiedDSCR equals readDSCR with bit
; DSCR[13] set
; select ITR
; Data Synchronization Barrier
; select DTR
Debug Test Access Port
14-31
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