Table 7-5 Summary Of Instruction Accesses To Tcm And Caches - ARM ARM1176JZF-S Technical Reference Manual

Data Data
TCM cache
Miss Hit
Miss Miss
Miss Miss
a. Excludes unexpected hit.
Instruction
TCM
Hit
Hit
Miss
Miss
a. Excludes unexpected hit.
ARM DDI 0301H
ID012310
Table 7-4 Summary of data accesses to TCM and caches (continued)
Instruction
Read behavior
TCM a
Miss Read from Data Cache.
Hit Read from Instruction TCM.
No cache fill even if marked
Cacheable.
Miss If Cacheable and cache
enabled, cache linefill.
If Noncacheable or cache
disabled, read to level two.
Table 7-5 summarizes the results of instruction accesses to TCM and the cache. This also
embodies the unexpected hit behavior for the cache that Unexpected hit behavior on page 7-6
describes. In Table 7-5, the Instruction Cache can only be hit if the memory location being
accessed is marked as being Cacheable and not shareable. A hit to the Instruction TCM refers
to hitting an address in the range covered by that TCM.
Instruction Data
TCM
cache a
Hit Don't care
Miss Don't care
Hit Don't care
Miss Don't care
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Write behavior
Write to Data Cache.
If Write-Through, write to level two.
Write to Instruction TCM.
No write to level two even if marked as
Write-Through.
Write to level two.

Table 7-5 Summary of instruction accesses to TCM and caches

Read behavior
Read from I TCMNo linefill to I Cache even if marked Cacheable
Read from Instruction TCM.
No linefill to Instruction Cache, even if marked cacheable.
Read from Instruction Cache.
If Cacheable and cache enabled, cache linefill.
If Noncacheable or cache disabled, read to level two.
Level One Memory System
7-15