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12.2.1
Synchronization of the VIC port signals
12.2.2
Interrupt handler exit
ARM DDI 0301H
ID012310
IRQADDRV is driven by a VIC to tell the processor that the address on the IRQADDR bus is
valid and being held, and so it is safe for the processor to sample it.
IRQACK and IRQADDRV together implement a four-phase handshake between the processor
and a VIC. See Timing of the VIC port on page 12-5 for more details.
The AHB system bus clock signal HCLK can run at any frequency, synchronously or
asynchronously to the processor clock signal, CLKIN. The processor VIC port can cope with
any clocking mode.
nFIQ and nIRQ can be connected to either synchronous or asynchronous sources.
Synchronizers are provided internally for the case of asynchronous sources. The Synchronous
Interrupt Enable port, INTSYNCEN, is also provided to enable SoC designers to bypass the
synchronizers if required. Similarly, a synchronizer is provided inside the processor for the
IRQADDRV signal. If this signal is known to be synchronous, the synchronizer can be
bypassed by pulling IRQADDRVSYNCEN HIGH.
These signals enable SoC designers to reduce interrupt latency if it is known that the nFIQ,
nIRQ, or IRQADDRV input is always driven by a synchronous source. When connecting the
PL192 VIC to the processor, INTSYNCEN must be tied LOW regardless of the clocking mode.
This is because the PL192 nVICIRQ and nVICFIQ outputs are completely asynchronous,
because there are combinational paths that cross this device through to these outputs. However,
IRQADDRVSYNCEN must be set depending on the clocking mode.
The software acknowledges an IRQ interrupt handler exit to a VIC by issuing a write to the
vector address register.
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Vectored Interrupt Controller Port
12-4
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