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39
DBGTDI
ARM DDI 0301H
ID012310
page 14-19, the Data field contains the data to be written and the
Ready/nRW bit holds the read/write information, 0=read and 1=write. If the
request is a read, the Data field is ignored.
•
When a request is placed, the Address and Data sections of the scan chain
are frozen. That is, their contents are not shifted until the request is
completed. This means that, if the value captured in the Ready/nRW field
at the Capture-DR state is 0, the shifted-in data is ignored and the
shifted-out value is all 0s.
•
After a read request has been placed, if the DBGTAPSM goes through the
Capture-DR state and a logic 1 is captured in the Ready/nRW field, this
means that the shift register has also captured the requested register
contents. Therefore, they are shifted out at the same time as the Ready/nRW
bit. The Data field is corrupted as new data is shifted in.
•
After a write request has been placed, if the DBGTAPSM goes through the
Capture-DR state and a logic 1 is captured in the Ready/nRW field, this
means that the requested write has completed successfully.
•
If the Address field is all 0s, address of the NULL register, at the
Update-DR state, then no request is generated.
•
A request to a reserved register generates Unpredictable behavior.
Order
Figure 14-13 shows the order of bits in scan chain 7.
33 32
Address[6:0]
A typical sequence for writing registers is as follows:
1.
Scan in the address of a first register, the data to write, and a 1 to indicate that this is a
write request.
2.
Scan in the address of a second register, the data to write, and a 1 to indicate that this is a
write request.
Scan out 40 bits. If Ready/nRW is 0, repeat this step. If Ready/nRW is 1, the first write
request has completed successfully and the second has been placed.
3.
Scan in the address 0. The rest of the fields are not important.
Scan out 40 bits. If Ready/nRW is 0, repeat this step. If Ready/nRW is 1, the second write
request has completed successfully. The scanned-in null request has avoided the
generation of another request.
A typical sequence for reading registers is as follows:
1.
Scan in the address of a first register and a 0 to indicate that this is a read request. The Data
field is not important.
2.
Scan in the address of a second register and a 0 to indicate that this is a read request.
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Data[31:0]
Figure 14-13 Scan chain 7 bit order
Debug Test Access Port
ReqCompl
1
0
DBGTDO
Ready/nRW
nRW
14-18
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