Table A-8 Peripheral Port Axi Signal Implementation - ARM ARM1176JZF-S Technical Reference Manual

Name
AWSIZEP[2:0]
AWBURSTP[1:0]
AWLOCKP[1:0]
AWCACHEP[3:0]
ARLENP[3:0]
ARSIZEP[2:0]
ARBURSTP[1:0]
ARLOCKP[1:0]
ARCACHEP[3:0]
ARSIDEBANDP[4:0]
AWSIDEBANDP[4:0]
A.5.4 DMA port signals
ARM DDI 0301H
ID012310
the read data bus is implemented as RDATAP[31:0]
•
the ARSIDEBANDP[4:0] output and AWSIDEBANDP[4:0] output signals are
•
implemented to indicate shared and inner cacheable accesses. These signals have fixed
values.
Table A-8 gives more information about the peripheral port AXI implementation. See the
AMBA ® AXI Protocol V1.0 Specification for details of the other signals on this port.
Direction Type
Output Write
Output Write
Output Write
Output Write
Output Read
Output Read
Output Read
Output Read
Output Read
Output Read
Output Write
The DMA port is a 64-bit wide read/write AXI port. The standard AXI read channel, write
channel, and write response channel signal names are suffixed with D, and the implementation
details of the port are:
AWID[3:0], WID[3:0], BID[3:0], ARID[3:0], and RID[3:0] signals are not
•
implemented
the write data bus is implemented as WDATAD[63:0], and therefore the write strobe
•
signal is implemented as WSTRBD[7:0]
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Table A-8 Peripheral port AXI signal implementation

Description
Write burst size:
b000, 8-bit transfers
b001, 16-bit transfers
b010, 32-bit transfers, maximum for the peripheral port.
Write burst type, always set to b01, INCR, Incrementing burst.
Write lock type, always set to b00, Normal access.
Cache type giving additional information about cacheable
characteristics for write accesses. Always set to 0x1.
Burst length that gives the exact number of transfer:
b0000, 1 data transfer
b0001, 2 data transfers.
Burst size:
b000, 8-bit transfer
b001, 16-bit transfer
b010, 32-bit transfer.
Read burst type, always set to b01, INCR, Incrementing burst.
Lock type:
b00, normal access
b10, locked transfer.
Cache type giving additional information about cacheable
characteristics. Always set to 0x1.
Indicates read accesses to shared and inner cacheable memory.
Always set to 0x2.
Indicates write accesses to shared and inner cacheable memory.
Always set to 0x2.
Signal Descriptions
A-10