System Control Register Summary; Table 4-1 System Control Registers - ARM Cortex-M0 Technical Reference Manual

4.2

System control register summary

Reset
Name
value
SYST_CSR -
SYST_RVR Unknown
SYST_CVR Unknown
SYST_CALIB
Implementation-defined
CPUID
0x410CC200
ICSR -
AIRCR
0x00000000
0x00008000
CCR -
SHPR2 -
SHPR3 -
SHCSR -
a. This value is configured by the implementer during implementation. See the documentation supplied by your implementer
for more information.
b. Little-endian implementation.
c. Big-endian implementation.
ARM DDI 0432C
ID112415
Table 4-1 gives the system control registers. Each of these registers is 32 bits wide.
Description
SysTick Control and Status Register in the ARMv6-M ARM
SysTick Reload Value Register in the ARMv6-M ARM
SysTick Current Value Register in the ARMv6-M ARM
SysTick Calibration value Register in the ARMv6-M ARM
a
See CPUID Register on page 4-4
Interrupt Control State Register in the ARMv6-M ARM
Application Interrupt and Reset Control Register in the ARMv6-M ARM
b
c
Configuration and Control Register in the ARMv6-M ARM
System Handler Priority Register 2 in the ARMv6-M ARM
System Handler Priority Register 3 in the ARMv6-M ARM
System Handler Control and State Register in the ARMv6-M ARM
Note
• All system control registers are only accessible using word transfers. Any attempt
to read or write a halfword or byte is Unpredictable.
• If the processor is implemented without the SysTick timer, the SYST_CSR,
SYST_RVR, SYST_CVR, and SYST_CALIB register reads as zero, writes
ignored RAZ/WI.
• See the ARMv6-M ARM for more information about the system control registers,
and their addresses and access types, and reset values not shown in Table 4-1.
Copyright © 2009 ARM Limited. All rights reserved.
Non-Confidential
System Control

Table 4-1 System control registers

4-3