Table 3-125 Interrupt Status Register Bit Functions; Table 3-126 Results Of Access To The Interrupt Status Register; Figure 3-67 Interrupt Status Register Format - ARM ARM1176JZF-S Technical Reference Manual

ARM DDI 0301H
ID012310
The Interrupt Status Register is:
• in CP15 c12
• a 32-bit read-only register common to Secure and Non-secure worlds
• accessible in privileged modes only.
Figure 3-67 shows the arrangement of bits in the register.
31
Table 3-125 lists how the bit values correspond with the Interrupt Status Register functions.
Note
The F and I bits directly reflect the state of the nFIQ and nIRQ pins respectively, but are
•
the inverse state.
• The A bit is set when an external abort occurs and automatically clears when the abort is
taken.
Table 3-126 lists the results of attempted access for each mode.
Secure Privileged
Read Write
Data Undefined exception
The A, I, and F bits map to the same format as the CPSR so that you can use the same mask for
these bits.
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SBZ

Figure 3-67 Interrupt Status Register format

Table 3-125 Interrupt Status Register bit functions

Bits Field name Function
[31:9] - SBZ.
[8] A Indicates when an external abort is pending:
0 = No abort, reset value
1 = Abort pending.
[7] I Indicates when an IRQ is pending:
0 = no IRQ, reset value
1 = IRQ pending.
[6] F Indicates when an FIQ is pending:
0 = no FIQ, reset value
1 = FIQ pending.
[5:0] - SBZ.
a. The reset values depend on external signals.

Table 3-126 Results of access to the Interrupt Status Register

Non-secure Privileged
Read Write
Data Undefined exception
System Control Coprocessor
9 8 7 6 5
A I F SBZ
a
User
Undefined exception
0
3-124