Table of Contents
Advertisement
VCR bit
VCR[1] = 1
VCR[2] = 1
VCR[3] = 1
VCR[4] = 1
VCR[6] = 1
VCR[7] = 1
VCR[10] = 1
VCR[11] = 1
VCR[12] = 1
VCR[14] = 1
VCR[15] = 1
VCR[25] = 1
VCR[26] = 1
VCR[27] = 1
VCR[28] = 1
ARM DDI 0301H
ID012310
Table 13-7 Summary of debug entry and exception conditions (continued)
NS bit, mode
NS bit = 0 or Mode = Secure
Monitor.
NS bit = 0 or Mode = Secure
Monitor.
NS bit = 0 or Mode = Secure
Monitor.
NS bit = 0 or Mode = Secure
Monitor.
NS bit = 0 or Mode = Secure
Monitor.
NS bit = 0 or Mode = Secure
Monitor.
NS bit = 0 or Mode = Secure
Monitor.
NS bit = 0 or Mode = Secure
Monitor.
NS bit = 0 or Mode = Secure
Monitor.
NS bit = 0 or Mode = Secure
Monitor.
NS bit = 0 or Mode = Secure
Monitor.
NS bit = 1 and mode ≠ Secure
Monitor
NS bit = 1 and mode ≠ Secure
Monitor
NS bit = 1 and mode ≠ Secure
Monitor
NS bit = 1 and mode ≠ Secure
Monitor
Copyright © 2004-2009 ARM Limited. All rights reserved.
Non-Confidential, Unrestricted Access
VE
HIVECS
Prefetch vector
X
0
SBA +
1
0xFFFF0004
X
0
SBA +
1
0xFFFF0008
X
0
SBA +
1
0xFFFF000C
X
0
SBA +
1
0xFFFF0010
0
0
SBA +
1
0xFFFF0018
1
X
Most recent Secure IRQ address
X
0
SBA +
1
0xFFFF001C
X
X
MBA +
X
X
MBA +
X
X
MBA +
X
X
MBA +
X
X
MBA +
X
0
NSBA +
1
0xFFFF0004
X
0
NSBA +
1
0xFFFF0008
X
0
NSBA +
1
0xFFFF000C
X
0
NSBA +
1
0xFFFF0010
Debug
0x00000004
0x00000008
0x0000000C
0x00000010
0x00000018
0x0000001C
0x00000008
0x0000000C
0x00000010
0x00000018
0x0000001C
0x00000004
0x00000008
0x0000000C
0x00000010
13-15
Hide quick links:
Advertisement
Table of Contents
