Figure 14-10 Scan Chain 5 Bit Order, Extest Selected; Figure 14-11 Scan Chain 5 Bit Order, Intest Selected - ARM ARM1176JZF-S Technical Reference Manual

EXTEST selected
DBGTDI
INTEST selected
DBGTDI
ARM DDI 0301H
ID012310
Scan chain 5
Purpose Debug.
Length 1 + 1 + 32 = 34 bits.
Description This scan chain accesses CP14 register c5, the data transfer registers, rDTR and
wDTR. The rDTR is used to transfer words from the DBGTAP debugger to the
core, and is read-only to the core and write-only to the DBGTAP debugger. The
wDTR is used to transfer words from the core to the DBGTAP debugger, and is
read-only to the DBGTAP debugger and write-only to the core.
The DBGTAP controller only sees one, read/write, register through scan chain 5,
and the appropriate register is chosen depending on the instruction used. INTEST
selects the wDTR, and EXTEST selects the rDTR.
Additionally, scan chain 5 contains some status flags. These are nRetry, Valid, and
Ready. They are the captured versions of the rDTRempty, wDTRfull, and
InstCompl flags respectively. All are captured at the Capture-DR state.
Order Figure 14-10 shows the order of bits in scan chain 5 with EXTEST selected.
Figure 14-11 shows the order of bits in scan chain 5 with INTEST selected.
33 32 31
rDTRempty InstCompl
nRetry Ready
33 32 31
wDTRfull InstCompl
Valid Ready
You can use scan chain 5 for two purposes:
• As part of the Debug Communications Channel (DCC). The DBGTAP debugger uses scan
chain 5 to exchange data with software running on the core. The software accesses the
rDTR and wDTR using coprocessor instructions.
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wDTR[31:0]
Data[31:0]
rDTR[31:0]

Figure 14-10 Scan chain 5 bit order, EXTEST selected

wDTR[31:0]
Data[31:0]

Figure 14-11 Scan chain 5 bit order, INTEST selected

Debug Test Access Port
0
DBGTDO
0
DBGTDO
14-15