ARM ARM1176JZF-S Technical Reference Manual page 120

2.12.11 Imprecise Data Abort mask in the CPSR/SPSR
2.12.12 Supervisor call instruction
2.12.13 Secure Monitor Call (SMC)
ARM DDI 0301H
ID012310
After dealing with the cause of the abort, the handler executes the following return instruction
irrespective of the processor operating state at the point of entry:
SUBS PC,R14_abt,#8
This restores both the PC and the CPSR, and retries the aborted instruction.
Imprecise Data Aborts
An imprecise Data Abort is signaled when the processor and system state presented to the abort
handler cannot be guaranteed to be consistent with the processor and system state when the
aborting instruction was issued.
An imprecise Data Abort caused, for example, by an External Error on a write that has been held
in a Write Buffer, is asynchronous to the execution of the causing instruction and can occur
many cycles after the instruction that caused the memory access has retired. For this reason, the
imprecise Data Abort can occur at a time that the processor is in Abort mode because of a
precise Data Abort, or can have live state in Abort mode, but be handling an interrupt.
To avoid the loss of the Abort mode state, R14_abt and SPSR_abt, in these cases, that leads to
the processor entering an unrecoverable state, the existence of a pending imprecise Data Abort
must be held by the system until a time when the Abort mode can safely be entered.
A mask is added into the CPSR to indicate that an imprecise Data Abort can be accepted. This
bit is referred to as the A bit. The imprecise Data Abort causes a Data Abort to be taken when
imprecise Data Aborts are not masked. When imprecise Data Aborts are masked, then the
implementation is responsible for holding the presence of a pending imprecise Data Abort until
the mask is cleared and the abort is taken. The A bit is set automatically on entry into Abort
Mode, IRQ, and FIQ Modes, and on Reset.
Note
You cannot change the CPSR A bit in the Non-secure world if the SCR bit 5 is reset. You can
change the SPSR A bit in the Non-secure world but this does not update the CPSR if the SCR
bit 5 does not permit it.
You can use the Supervisor call instruction (SVC) to enter Supervisor mode, usually to request
a particular supervisor function. The SVC handler reads the opcode to extract the SVC function
number. A SVC handler returns by executing the following instruction, irrespective of the
processor operating state:
MOVS PC, R14_svc
This action restores the PC and CPSR, and returns to the instruction following the SVC.
IRQs are disabled when a Supervisor call occurs.
When the processor executes the Secure Monitor Call (SMC) the core enters Secure Monitor
mode to execute the Secure Monitor code. For more details on SMC and the Secure Monitor,
see The NS bit and Secure Monitor mode on page 2-4.
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