Table 3-9 Tcm Status Register Bit Functions; Figure 3-12 Tcm Status Register Format - ARM ARM1176JZF-S Technical Reference Manual

3.2.4 c0, TCM Status Register
ARM DDI 0301H
ID012310
The purpose of the TCM Status Register is to inform the system about the number of Instruction
and Data TCMs available in the processor.
Table 3-9 lists the purposes of the individual bits in the TCM Status Register.
Note
In the ARM1176JZF-S processor there is a maximum of two Instruction TCMs and two Data
TCMs.
The TCM Status Register is:
• in CP15 c0
• a 32-bit read-only register common to Secure and Non-secure worlds
• accessible in privileged modes only.
Figure 3-12 shows the bit arrangement for the TCM Status Register.
31 30 29 28
0 0 0 SBZ/UNP
Table 3-9 lists how the bit values correspond with the TCM Status Register functions.
Bits Field name
[31:29] -
[28:19] -
[18:16] DTCM
[15:3] -
[2:0] ITCM
Attempts to write the TCM Status Register or read it in User modes result in Undefined
exceptions.
To use the TCM Status Register read CP15 with:
• Opcode_1 set to 0
• CRn set to c0
• CRm set to c0
• Opcode_2 set to 2.
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19 18 16 15
DTCM SBZ/UNP

Figure 3-12 TCM Status Register format

Table 3-9 TCM Status Register bit functions

Function
Always b000.
UNP/SBZ
Indicates the number of Data TCM banks implemented.
b000 = 0 Data TCMs
b001 = 1 Data TCM
b010 = 2 Data TCMs
All other values reserved
UNP/SBZ
Indicates the number of Instruction TCM banks implemented.
b000 = 0 Instruction TCMs
b001 = 1 Instruction TCM
b010 = 2 Instruction TCMs
All other values reserved
System Control Coprocessor
3 2 0
ITCM
3-24