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Bits
Reset value
[31:7]
UNP/SBZ
[6]
0
[5]
UNP/SBZ
[4]
0
[3]
0
[2]
0
[1]
0
[0]
0
ARM DDI 0301H
ID012310
Table 13-18 Debug State MMU Control Register bit functions
Name
Description
-
Reserved
nDMM
1 = Normal operation of Main TLB matching in Debug state.
0 = Main TLB match disabled in Debug state.
-
Reserved
nDML
1 = Normal operation of Main TLB loading in Debug state.
0 = Main TLB load disabled in Debug state.
nIUM
1 = Normal operation of Instruction Micro TLB matching in Debug state.
0 = Instruction Micro TLB match disabled in Debug state.
nDUM
1 = Normal operation of Data Micro TLB matching in Debug state.
0 = Data Micro TLB match disabled in Debug state.
nIUL
1 = Normal operation of Instruction Micro TLB loading and flushing in Debug state.
0 = Instruction Micro TLB load and flush disabled in Debug state.
nDUL
1 = Normal operation of Data Micro TLB loading and flushing in Debug state.
0 = Data Micro TLB load and flush disabled in Debug state.
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Debug
13-24
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