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Read/Write
Bits
Attributes
[31]
RW
[30]
RW
[29]
DNM/RAZ
[28]
RW
[27]
RW
[26]
RW
[25]
RW
[24:16]
DNM/RAZ
[15]
RW
[14]
RW
[13]
DNM/RAZ
[12]
RW
[11]
RW
[10]
RW
[9:8]
DNM/RAZ
[7]
RW
[6]
RW
[5]
DNM/RAZ
[4]
RW
[3]
RW
[2]
RW
[1]
RW
[0]
RW
VCR bit
VCR[0] = 1
ARM DDI 0301H
ID012310
Table 13-7 lists the conditions for generation of a Debug exception or entry into Debug State. In
this table, SBA means Secure Base Address, NSBA means Non-Secure Base Address, MBA
means Monitor Base Address.
Reset
Vector base
value
0
NSBA
0
NSBA
0
-
0
NSBA
0
NSBA
0
NSBA
0
NSBA
0
-
0
MBA
0
MBA
0
-
0
MBA
0
MBA
0
MBA
0
-
0
SBA
0
SBA
0
-
0
SBA
0
SBA
0
SBA
0
SBA
0
SBA
NS bit, mode
NS bit = 0 or Mode = Secure
Monitor.
Copyright © 2004-2009 ARM Limited. All rights reserved.
Non-Confidential, Unrestricted Access
Table 13-6 Vector Catch Register bit field definitions
Description
Vector Catch Enable - FIQ in Non-secure world.
Vector Catch Enable - IRQ in Non-secure world.
Reserved
Vector Catch Enable - Data Abort in Non-secure world.
Vector Catch Enable - Prefetch Abort in Non-secure world.
Vector Catch Enable - SVC in Non-secure world.
Vector Catch Enable - Undefined Instruction in Non-secure
world.
Reserved
Vector Catch Enable - FIQ in Secure world.
Vector Catch Enable - IRQ in Secure world.
Reserved
Vector Catch Enable - Data Abort in Secure world.
Vector Catch Enable - Prefetch Abort in Secure World
Vector Catch Enable - SMC in Secure world.
Reserved
Vector Catch Enable - FIQ in Secure world.
Vector Catch Enable - IRQ in Secure world.
Reserved
Vector Catch Enable - Data Abort in Secure world.
Vector Catch Enable - Prefetch Abort in Secure world.
Vector Catch Enable, SVC in Secure world.
Vector Catch Enable, Undefined Instruction in Secure world.
Vector Catch Enable, Reset
Table 13-7 Summary of debug entry and exception conditions
VE
HIVECS
X
0
1
Prefetch vector
0x00000000
0xFFFF0000
Debug
13-14
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