Table 13-25 Read Pc Value After Debug State Entry - ARM ARM1176JZF-S Technical Reference Manual

Debug event
Breakpoint
Watchpoint
BKPT instruction
Vector catch
External debug request signal
activation
Debug state entry request
command
a. This is the address of the instruction that the processor first executes on Debug state exit. Watchpoints can be imprecise. RA
is not the address of the instruction immediately after the one that hit the watchpoint, the processor might stop a number of
instructions later. The address of the instruction that hit the watchpoint is in the CP15 WFAR.
13.10.2 Interrupts
13.10.3 Exceptions
ARM DDI 0301H
ID012310
• If the PC is read after the processor has entered Debug state, it returns a value as
Table 13-25 lists, depending on the previous state and the type of debug event.
• If a sequence for writing a certain value to the PC is executed while in Debug state, and
then the processor is forced to restart, execution starts at the address corresponding to the
written value. However, the CPSR has to be set to the return ARM, Thumb, or Jazelle state
before the PC is written to, otherwise the processor behavior is Unpredictable.
• If the processor is forced to restart without having performed a write to the PC, the restart
address is Unpredictable.
• If the PC or CPSR are written to while in Debug state, subsequent reads to the PC return
an Unpredictable value.
• The MSR instruction has an Unpredictable effect on the PC so the PC must be written
before leaving Debug state.
• If a conditional branch is executed and it fails its condition code, an Unpredictable value
is written to the PC.
Table 13-25 lists the read PC value after Debug state entry for different debug events.
ARM Thumb
RA+8 RA+4
RA+8 RA+4
RA+8 RA+4
RA+8 RA+4
RA+8 RA+4
RA+8 RA+4
Interrupts are ignored regardless of the value of the I and F bits of the CPSR, although these bits
are not changed because of the Debug state entry.
Exceptions are handled as follows while in Debug state:
Reset This exception is taken as in a normal processor state, ARM, Thumb, or Jazelle.
This means the processor leaves Debug state as a result of the system reset.
Prefetch Abort
This exception cannot occur because no instructions are prefetched while in
Debug state.
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Table 13-25 Read PC value after Debug state entry

Jazelle Return address (RA
RA Breakpointed instruction address
RA Address of the instruction where the execution
resumes, several instructions after the one that hit the
watchpoint
RA BKPT instruction address
RA Vector address
RA Address of the instruction where the execution
resumes
RA Address of the instruction where the execution
resumes
Debug
a ) meaning
13-39