Table 13-22 Behavior Of The Processor On Debug Events - ARM ARM1176JZF-S Technical Reference Manual

13.8.3 Halt DBGTAP instruction
13.8.4 Behavior of the processor on debug events
DBGEN DSCR[15:14]
0 bxx
1 b00
1 b01
1 b10
1 b11
a. Entry to Debug state is disabled.
b. When no debug mode is selected and enabled or the core is in a state that does not permit debug, a BKPT instruction generates
a Prefetch Abort exception instead of being ignored.
c. Prefetch Abort and Data Abort vector catch debug events are ignored in Monitor debug-mode. Unlinked context ID and
address mismatch breakpoint debug events are also ignored if the processor is running in a privileged mode and Monitor
debug-mode is selected and enabled.
ARM DDI 0301H
ID012310
fault occurs, an external Trace analyzer can collect trace information around this trigger event
at the same time that the processor is stopped to examine its state. See the Chapter 15 Trace
Interface Port for more details. A DBGTAP debugger can also drive this signal.
The Halt mechanism is used by the Debug Test Access Port to force the core into Debug state.
When this happens, the DSCR[5:2] method of entry bits are set to b0000.
This section describes how the processor behaves on debug events while not in Debug state. See
Debug state on page 13-37 for information on how the processor behaves while in Debug state.
When a software debug event occurs and Monitor debug-mode is selected and enabled and the
core is in a state that permits debug then a Debug exception is taken. However, Prefetch Abort
and Data Abort Vector catch debug events are ignored.
This is to avoid the processor ending in an unrecoverable state on certain combinations of
exceptions and vector catches. Unlinked context ID and all address mismatch breakpoint debug
events are also ignored if the processor is running in a privileged mode and Monitor debug-mode
is selected and enabled.
When the external debug request signal is activated, or the DBGTAP instruction is issued and
debug is enabled by DBGEN and the core is in a state that permits debug, the processor enters
Debug state regardless of any debug-mode selected by DSCR[15:14].
When a debug event occurs and Halting debug-mode is selected and enabled and the core is in
a state that debug is permitted, then the processor enters Debug state.
All software debug events other than the BKPT instruction, that is register breakpoints,
watchpoints, and vector catches, when no debug mode is selected and enabled or the core is in
a state that does not permit debug, are ignored.
When neither Halting nor Monitor debug-mode is selected and enabled or the core is in a state
that does not permit debug, the BKPT instruction generates a Prefetch Abort exception.
Table 13-22 lists the behavior of the processor in debug events.
Mode
selected,
enabled and
permitted
a
-
None
Halting
Monitor
Halting
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Table 13-22 Behavior of the processor on debug events

Action on external
Action on software
debug request
debug event
signal activation
b Ignore
Ignore/Prefetch Abort
a Debug state entry
Ignore/Prefetch Abort
Debug state entry Debug state entry
Debug Debug state entry
c
exception/Ignore
Debug state entry Debug state entry
Debug
Action on Halt
DBGTAP
Ignore
Debug state entry
Debug state entry
Debug state entry
Debug state entry
13-33