ARM ARM1176JZF-S Technical Reference Manual page 564

14.8.15 Reading memory as halfwords or bytes
14.8.16 Writing memory as halfwords/bytes
14.8.17 Coprocessor register reads and writes
ARM DDI 0301H
ID012310
UNTIL Ready==1
4. Check for aborts, as Reading memory as words on page 14-36 describes.
The above sequences cannot be used to transfer halfwords or bytes because LDC and STC
instructions always transfer whole words. Two operations are required to complete a halfword
or byte transfer, from memory to ARM register and from ARM register to CP14 debug register.
Therefore, performance is decreased because the load instruction cannot be kept in the ITR. This
sequence assumes that R0 has been set to the address to load data from prior to running the
sequence. Register R0 is post-incremented so that it can be used by successive reads of memory.
Register R1 is used as a temporary register:
1. Load and issue the LDRH or LDRB instruction:
ITRSEL
INST LDRH R1,[R0],#2
RTI
LOOP
INST 0x00000000 Ready
UNTIL Ready==1
2. Use the standard sequence that Reading a current mode ARM register in the range R0-R14
on page 14-34 describes on register R1. Now scan chain 5 and INTEST are selected.
3. If there are more halfwords or bytes to be read go to 1.
4. Check for aborts, as Reading memory as words on page 14-36 describes.
This sequence assumes that R0 has been set to the address to store data to prior to running this
sequence. Register R0 is post-incremented so that it can be used by successive writes to memory.
Register R1 is used as a temporary register:
1. Write the halfword/byte onto R1 using the standard sequence that Writing a current mode
ARM register in the range R0-R14 on page 14-34 describes. Scan chain 5 and EXTEST
are selected.
2. Write the contents of R1 to memory:
ITRSEL
INST STRH R1,[R0],#2
RTI
LOOP
INST 0x00000000 Ready
UNTIL Ready==1
3. If there are more halfwords or bytes to be read go to 1.
4. Now check for aborts as Reading memory as words on page 14-36 describes.
The processor can execute coprocessor instructions while in Debug state. Therefore, the
straightforward method to transfer data between a coprocessor and the DBGTAP debugger is
using an ARM register temporarily. For this method to work, the coprocessor must be able to
transfer all its registers to the core using coprocessor transfer instructions.
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; wait until instruction ends
; select the ITR and EXTEST
; LDRB R1,[R0],#1 for byte reads
; wait until instruction ends
; select the ITR and EXTEST
; STRB R1,[R0],#1 for byte writes
; wait until instruction ends
Debug Test Access Port
14-38