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4.1
About unaligned and mixed-endian support
ARM DDI 0301H
ID012310
The processor executes the ARM architecture v6 instructions that support mixed-endian access
in hardware, and assist unaligned data accesses. The extensions to ARMv6 that support
unaligned and mixed-endian accesses include the following:
•
CP15 Register c1 has a U bit that enables unaligned support. This bit was specified as zero
in previous architectures, and resets to zero for legacy-mode compatibility.
•
Architecturally defined unaligned word and halfword access specification for hardware
implementation.
•
Byte reverse instructions that operate on general-purpose register contents to support
signed/unsigned halfword data values.
•
Separate instruction and data endianness, with instructions fixed as little-endian format,
naturally aligned, but with legacy support for 32-bit word-invariant binary images and
ROM.
•
A PSR endian control flag, the E-bit, set to the value of the EE bit on exception entry, see
c1, Control Register on page 3-44, that adds a byte-reverse operation to the entire load and
store instruction space as data is loaded into and stored back out of the register file. In
previous architectures this Program Status Register bit was specified as zero. It is not set
in legacy code written to conform to architectures prior to ARMv6.
•
ARM and Thumb instructions to set and clear the E-bit explicitly.
•
A byte-invariant addressing scheme to support fine-grain big-endian and little-endian
shared data structures, to conform to a shared memory standard.
The original ARM architecture was designed as little-endian. This provides a consistent address
ordering of bits, bytes, words, cache lines, and pages, and is assumed by the documentation of
instruction set encoding and memory and register bit significance. Subsequently, big-endian
support was added to enable big-endian byte addressing of memory. A little-endian
nomenclature is used for bit-ordering and byte addressing throughout this manual.
Note
In the TrustZone architecture you can only modify the B bit in the Secure world. The A, U and
EE bits are banked for the Secure and Non-secure worlds, see c1, Control Register on page 3-44.
This means that you can only change the endian behavior of the memory system of the
processor, that the B bit controls, in the Secure world. The B bit is expected to have a static
value.
Unaligned data access, that the U bit controls, the value of the E bit in the CPSR on exceptions,
that the EE bit controls, and strict alignment of data, that the A bit controls, can differ in the
Secure and Non-secure worlds.
Copyright © 2004-2009 ARM Limited. All rights reserved.
Non-Confidential, Unrestricted Access
Unaligned and Mixed-endian Data Access Support
4-2
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