Table 15-2 Etmiactl[17:0] - ARM ARM1176JZF-S Technical Reference Manual

Bits Reference name
IASlotKill
[17]
IADAbort
[16]
IAExCancel
[15]
IAExInt
[12:14]
IAException
[11]
IABounce
[10]
IADataInst
[9]
IAContextID
[8]
IAIndBr
[7]
IABpCCFail
[6]
IAInstCCFail
[5]
IAJBit
[4]
IATBit
[3]
IABpValid
[2]
IAInstValid
[1]
IAValid
[0]
a. The exception signals become valid when the core takes the exception and remain valid until the next instruction is seen at the
exception vector.
ARM DDI 0301H
ID012310
ETMIABP = ETMIA - <isize>
Table 15-2 lists the ETMIACTL[17:0] instruction interface control signals.
Description
Kill outstanding slots.
Data Abort.
Exception canceled previous instruction.
b001 = IRQb101 = FIQb100 = Java exception b110 = Precise Data
Abortb000 = Other exception.
Instruction is an exception vector.
Kill the data slot associated with this instruction. There is only ever
one of these instructions. Used for bouncing coprocessor instructions.
Instruction is a data instruction. This includes any load, store, or
CPRT, but does not include preloads.
Instruction updates context ID.
Instruction is an indirect branch.
Branch phantom failed its condition codes.
Instruction failed its condition codes.
Instruction executed in Jazelle state.
Instruction executed in Thumb state.
Branch phantom executed this cycle.
(Non-phantom) instruction executed this cycle.
Signals on the instruction interface are valid this cycle. This is kept
LOW when the ETM is powered down.
Exception reporting
The ARM1176JZF-S Trace Interface Port is designed for ETMs that support ETMv3.2 or above.
ETMv3.2 permits the determination of each type of exception without reference to the
destination address in the branch packet.
The ETM protocol does not permit the indication of an exception before the first instruction is
traced. If the first instruction traced, when turning on trace, is the instruction at an exception
vector, then the trace does not report an exception. Normally this is not a concern, because you
can expect some missing trace when the trace is turned off.
However, there are two occasions where trace is turned off automatically, so that trace might
lose exceptions even when the ETM is configured to trace continuously:
• the processor enters Debug state
• the processor enters a region where tracing is prohibited, a prohibited region.
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Trace Interface Port

Table 15-2 ETMIACTL[17:0]

Qualified by
IAException
IAException
IAException
IAException
a
None
IADataInst
IAInstValid
IAInstValid
IAInstValid
IABpValid
IAInstValid
IAValid
IAValid
IAValid
IAValid
None
15-3