Figure 3-3 Cache Control And Configuration Registers; Figure 3-4 Tcm Control And Configuration Registers - ARM ARM1176JZF-S Technical Reference Manual

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3.1.5
TCM control and configuration
3.1.6
Cache Master Valid Registers
ARM DDI 0301H
ID012310
CRn
Opcode_1
c0
0
c7
0
c9
0
Read-only
To use the system control and configuration registers you read or write individual registers that
make up the group, see Use of the system control coprocessor on page 3-12.
Cache control and configuration registers behave as:
a set of numbers, values that describe aspects of the caches
a set of bits that enable specific cache functionality
a set of operations that act on the caches.
The purpose of the TCM control and configuration registers is to:
inform the processor about the status of the TCM regions
define TCM regions.
The TCM control and configuration registers consist of one 32-bit read-only register and five
32-bit read/write registers. Figure 3-4 shows the arrangement of registers.
CRn
Opcode_1
CRm
c0
0
c0
c9
0
c1
c2
Read-only
To use the system control and configuration registers you read or write individual registers that
make up the group, see Use of the system control coprocessor on page 3-12.
TCM control and configuration behaves in three ways:
as a set of numbers, values that describe aspects of the TCMs
as a set of bits that enable specific TCM functionality
as a set of addresses that define the memory locations of data stored in the TCMs.
The purpose of the Cache Master Valid Registers is to hold the state of the Master Valid bits of
the instruction and data caches.
The cache debug registers consist of two 32-bit read/write registers. Figure 3-5 on page 3-9
shows the arrangement of registers in this functional group.
Copyright © 2004-2009 ARM Limited. All rights reserved.
Non-Confidential, Unrestricted Access
CRm
Opcode_2
c0
1
c0
0
1
0
c8
Read/write

Figure 3-3 Cache control and configuration registers

Opcode_2
TCM Status Register
2
0
Data TCM Region Register
1
Instruction TCM Region Register
2
Data TCM Non-secure Access Control Register
3
Instruction TCM Non-secure Access Control Register
0
TCM Selection Register
Read/write
Write-only

Figure 3-4 TCM control and configuration registers

System Control Coprocessor
Cache Type Register
Cache Operations Register
Data Cache Lockdown Register
Instruction Cache Lockdown Register
Cache Behavior Override Register
Write only
Accessible in User mode
Accessible in User mode
3-8

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