ARM ARM1176JZF-S Technical Reference Manual page 16

Table 21-15 Parallel execution in all three pipelines ................................................................................... 21-21
Table 21-16 Throughput and latency cycle counts for VFP11 instructions ................................................. 21-22
Table 22-1 Exceptional short vector FMULD followed by load/store instructions ....................................... 22-9
Table 22-2 Exceptional short vector FADDS with a FADDS in the pretrigger slot .................................... 22-10
Table 22-3 Exceptional short vector FADDD with an FMACS trigger instruction ...................................... 22-11
Table 22-4 Possible Invalid Operation exceptions .................................................................................... 22-13
Table 22-5 Default results for invalid conversion inputs ............................................................................ 22-14
Table 22-6 Rounding mode overflow results ............................................................................................. 22-16
Table 22-7 LSA and USA determination ................................................................................................... 22-20
Table 22-8 FADD family bounce thresholds ............................................................................................. 22-21
Table 22-9 FMUL family bounce thresholds ............................................................................................. 22-22
Table 22-10 FDIV bounce thresholds ......................................................................................................... 22-23
Table 22-11 FCVTSD bounce thresholds ................................................................................................... 22-24
Table 22-12 Single-precision float-to-integer bounce thresholds and stored results .................................. 22-25
Table 22-13 Double-precision float-to-integer bounce thresholds and stored results ................................. 22-26
Table A-1 Global signals ............................................................................................................................. A-2
Table A-2 Static configuration signals ......................................................................................................... A-4
Table A-3 TrustZone internal signals ........................................................................................................... A-5
Table A-4 Interrupt signals .......................................................................................................................... A-6
Table A-5 Port signal name suffixes ............................................................................................................ A-7
Table A-6 Instruction read port AXI signal implementation ......................................................................... A-8
Table A-7 Data port AXI signal implementation ........................................................................................... A-9
Table A-8 Peripheral port AXI signal implementation ................................................................................ A-10
Table A-9 DMA port signals ....................................................................................................................... A-11
Table A-10 Core to coprocessor signals ..................................................................................................... A-12
Table A-11 Coprocessor to core signals ..................................................................................................... A-12
Table A-12 Debug interface signals ............................................................................................................ A-14
Table A-13 ETM interface signals ............................................................................................................... A-15
Table A-14 Test signals ............................................................................................................................... A-16
Table B-1 TCM for ARM1176JZF-S processors .......................................................................................... B-6
Table B-2 CP15 c15 features common to ARM1136JF-S and ARM1176JZF-S processors ...................... B-8
Table B-3 CP15 c15 only found in ARM1136JF-S processors .................................................................... B-9
Table C-1 Differences between issue G and issue H .................................................................................. C-1
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