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1.1
About the processor
ARM DDI 0301H
ID012310
The ARM1176JZF-S processor incorporates an integer core that implements the ARM11 ARM
architecture v6. It supports the ARM and Thumb
direct execution of Java bytecodes, and a range of SIMD DSP instructions that operate on 16-bit
or 8-bit data values in 32-bit registers.
The ARM1176JZF-S processor features:
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•
TrustZone
security extensions
•
provision for Intelligent Energy Management (IEM
•
high-speed Advanced Microprocessor Bus Architecture (AMBA) Advanced Extensible
Interface (AXI) level two interfaces supporting prioritized multiprocessor
implementations.
•
an integer core with integral EmbeddedICE-RT logic
•
an eight-stage pipeline
•
branch prediction with return stack
•
low interrupt latency configuration
•
internal coprocessors CP14 and CP15
•
Vector Floating-Point (VFP) coprocessor support
•
external coprocessor interface
•
Instruction and Data Memory Management Units (MMUs), managed using MicroTLB
structures backed by a unified Main TLB
•
Instruction and data caches, including a non-blocking data cache with Hit-Under-Miss
(HUM)
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virtually indexed and physically addressed caches
•
64-bit interface to both caches
•
level one Tightly-Coupled Memory (TCM) that you can use as a local RAM with DMA
•
trace support
•
JTAG-based debug.
Note
The only functional difference between the ARM1176JZ-S and ARM1176JZF-S processor is
that the ARM1176JZF-S processor includes a Vector Floating-Point (VFP) coprocessor.
Copyright © 2004-2009 ARM Limited. All rights reserved.
Non-Confidential, Unrestricted Access
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instruction sets, Jazelle technology to enable
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)
Introduction
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